High Level Synthesis tool for FPGA using NoCs.
Project description
SyntheSys
=========
SyntheSys is a Python module for generating network on chip (NoC) based systems from Python3 programs. It is specially design for reconfigurable computing, i.e. using FPGA to accelerate parts of programs. It has a extensible library for any type of FPGA and uses NoC properties to be scalable.
This is the README file for the project.
----
SyntheSys is distributed with a GPLv3 license.
See LICENSE.txt for details.
----
Matthieu PAYET <matthieu.payet@free.fr>
More on Matthieu's website : mpayet.net
=========
SyntheSys is a Python module for generating network on chip (NoC) based systems from Python3 programs. It is specially design for reconfigurable computing, i.e. using FPGA to accelerate parts of programs. It has a extensible library for any type of FPGA and uses NoC properties to be scalable.
This is the README file for the project.
----
SyntheSys is distributed with a GPLv3 license.
See LICENSE.txt for details.
----
Matthieu PAYET <matthieu.payet@free.fr>
More on Matthieu's website : mpayet.net
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Hashes for SyntheSys-0.1.1.linux-x86_64.tar.gz
Algorithm | Hash digest | |
---|---|---|
SHA256 | a7571b4e6327e4267f31d5315057f09a9f08214ad51d9f73f342ecfb59e98b5b |
|
MD5 | 0d96df01185fc02f1a08b8b1d8caaff0 |
|
BLAKE2b-256 | 2a4848511cc4494ac35aa23f2c63f0520652e0913c41ea4ea0324fc31ccd66ad |
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Hashes for SyntheSys-0.1.1-py3-none-any.whl
Algorithm | Hash digest | |
---|---|---|
SHA256 | b1ac56dc0192af33c87b03a67fe1095155161220a9fcf023a16ae4a391194a27 |
|
MD5 | da663d31032d9d3bafb8dd01bd9afada |
|
BLAKE2b-256 | d3476c834714a8705fd9c3c016059d1f845c5c618679bbc5a8c34b1ce20d0c6a |