PDKMaster based scalable standard cell library
Flexible, scalable, standard cell library
A standard cell library is a collection of cells that perform certain digital functions. It consists of so-called combinatorial cells which perform a binary logic function and sequential cells sync internal signal with a clock signal.
Standard cells are introduced into an ASIC EDA flow during the synthesis step. This is the step where a (RTL) logic design into a netlist consisting only of the cells from your standard cell library. Later on these cells are then placed next to each and the inputs and outputs of each cell connected to each other. The former is called placement and the latter routing.
Up to now for a lot of standard cell libraries the layout was done manually leading to a lot manual work when changes need to be done like changing the height of the cells or porting it to another technology node. Some of them are based on so-called lambda rules to make them scalable to different nodes. Usage of lambda rules will cause their own inefficiencies in the layout especially when scaling to smaller nodes.
Alternative implementations try to fully automate the layout generation out of the transistor netlist. Finding a good placement of the transistor for non-trivial logic cells is a hard problem leading often to complex code for finding acceptable solutions. Also the layout code itself often becomes complex to take peculiarities of different design rules into account.
flexcell library tries to take a middle road. It will start from a topological layout of the cell but without the layout already fixed to certain design rules; it thus avoid the step where netlist need to be converted to topologies. It will use the design rules from a PDKMaster Technology object to generate an optimized layout for conforming to the cells topology. By baking in independence of the Technology the standard cell library should be easily ported to different technologies with better area efficiency than current lambda rules based solutions.
In future options are planned so libraries can be generated for different targets like ,minimum area, maximum performance or minimum power consumption.
This repository is currently considered experimental code with no backwards compatibility guarantees whatsoever.
Current implementation is based on the topology of the Coriolis nsxlib standard cells with some area improvements but not yet with optimal area use. For v0.1 of this library a total replacement of the layout generation is planned fully based on minimized area for the technology design rules.
If interested head over to gitter for further discussion.
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