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creator for Reconfigurable Component. Framework and Code generator for FPGA component

Project description


creator for Reconfigurable hw Component

Author: Kazushi Yamashina (Utsunomiya University)
Copyright: 2016, Kazushi Yamashina
License: new BSD License
Latest Version: 1.0.0
Contact: or Twitter or Facebook

What is the cReComp?

The cReComp is a code generator and framework for componentization of a single hardware or the multiple hardware. The component generated by the cReComp is HW/SW co-system that is connected between CPU and FPGA (reconfigurable hw). The cReComp is possible to debug and test single hardware with software in a user development fase. When the development of a each hardware have been finished, the cReComp generates one of the HW/SW co-system by integrating the each of the hardware.


2016/06/30 released version 1.0.0




Ubuntu or OSX (Mac)

Python (2.7 later)

sudo apt-get install python

Icarus Verilog


sudo apt-get install iverilog


brew install icarus-verilog


pip install jinja2


git clone
cd pyverilog/
python install


git clone
cd veriloggen/
python install

Install cReComp

Download from github & install

git clone
cd cReComp/
python install

Package install

pip install crecomp

Command usage

Usage: python crecomp [-t] [-u user logic]+

  -h, --help            show this help message and exit
  -u USERLOGIC, --userlogic=USERLOGIC
                        specifier your user logic name
                        specifier for template name

Project details

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Source Distribution

crecomp-1.0.0.tar.gz (23.8 kB view hashes)

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