creator for Reconfigurable Component. Framework and Code generator for FPGA component
creator for Reconfigurable hw Component
What is the cReComp?
The cReComp is a code generator and framework for componentization of a single hardware or the multiple hardware. The component generated by the cReComp is HW/SW co-system that is connected between CPU and FPGA (reconfigurable hw). The cReComp is possible to debug and test single hardware with software in a user development fase. When the development of a each hardware have been finished, the cReComp generates one of the HW/SW co-system by integrating the each of the hardware.
2016/06/30 released version 1.0.0
Ubuntu or OSX (Mac)
Python (2.7 later)
sudo apt-get install python
sudo apt-get install iverilog
brew install icarus-verilog
pip install jinja2
git clone https://github.com/PyHDI/pyverilog.git cd pyverilog/ python setup.py install
git clone https://github.com/PyHDI/veriloggen.git cd veriloggen/ python setup.py install
Download from github & install
git clone https://github.com/kazuyamashi/cReComp.git cd cReComp/ python setup.py install
pip install crecomp
Usage: python crecomp [-t] [-u user logic]+ Options: -h, --help show this help message and exit -u USERLOGIC, --userlogic=USERLOGIC specifier your user logic name -t TEMPLATENAME, --template=TEMPLATENAME specifier for template name
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