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generate verilog module testbench

Project description

gen_tb

介绍

自动生成verilog module testbench 模板的工具

安装教程

无需安装

windows下使用说明

  1. 直接使用gen_tb.exe

将.v文件和gen_tb.exe放在同一路径,双击gen_tb.exe,根据提示输入文件名,回车即可。

当一个.v文件中含有多个module时只会例化第一个。

  1. 使用命令

输入图片说明

  1. 使用脚本

输入图片说明

请注意使用对应的解释器版本:

gen_tb.cp312-win_amd64.pyd 对应的python版本为3.12

linux下使用说明

下次更新

其他说明

若发现bug可联系我修复。

Project details


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