FPGA ultra low latency options triggering
Project description
gg-fpga
FPGA / Python Simulation and Output focused on exchange binary protocol parsing and specifics of byte layout for msg types
uses SystemVerilog and Python and currently supports interfacing
with excel and matplotlib.pyplot
Note:
Currently set up to only work on Linux platforms
In addition to dependencies in pyproject, also requires:
- iverilog
And, for simulation:
- verilator (only easily available for Linux systems)
Download files
Download the file for your platform. If you're not sure which to choose, learn more about installing packages.
Source Distribution
gg_fpga-0.0.14.tar.gz
(4.3 MB
view details)
Built Distribution
File details
Details for the file gg_fpga-0.0.14.tar.gz.
File metadata
- Download URL: gg_fpga-0.0.14.tar.gz
- Upload date:
- Size: 4.3 MB
- Tags: Source
- Uploaded using Trusted Publishing? No
- Uploaded via: twine/5.1.1 CPython/3.12.3
File hashes
| Algorithm | Hash digest | |
|---|---|---|
| SHA256 | dbe9f764d572bc204ec68453df3212beb92c68a5ceaf1c6d00c4be41f3802d4e |
|
| MD5 | 24d179ca9fb134684492946926e97240 |
|
| BLAKE2b-256 | e3098aa02b351823070ed035d8b2bea4f9595cac466ecb2a2cd3f6135aa55b23 |
File details
Details for the file gg_fpga-0.0.14-py3-none-any.whl.
File metadata
- Download URL: gg_fpga-0.0.14-py3-none-any.whl
- Upload date:
- Size: 4.4 MB
- Tags: Python 3
- Uploaded using Trusted Publishing? No
- Uploaded via: twine/5.1.1 CPython/3.12.3
File hashes
| Algorithm | Hash digest | |
|---|---|---|
| SHA256 | fe8a27ad4c4499ab55c6b07a2aaea2025fb9e3cb581d2a883ef0b3c8e4110346 |
|
| MD5 | 1496486a9783583ddbb7a6341c6f5cf5 |
|
| BLAKE2b-256 | 88a5e168a24aa8693802de5bfe382992dca31d0b3e6c163b29366ae78026e187 |
