An open-source HDL register interface code generator fast enough to run in real time
Project description
The hdl-registers project is an open-source HDL register interface code generator fast enough to run in real time. It makes FPGA/ASIC development more fun by automating a lot of time-consuming manual work. It also minimizes the risk of bugs by removing the need for duplicate information. Read more
See documentation on the website: https://hdl-registers.com
Check out the source code on GitHub: https://github.com/hdl-registers/hdl-registers
The following features are supported:
Register fields
Registers can be defined using a TOML/JSON/YAML data file or the Python API. The following code can be generated:
-
AXI-Lite register file wrapper using records and native VHDL types for values.
Support packages for compact and efficient simulation.
-
Complete class with setters and getters for registers and fields.
Includes an abstract interface header for unit test mocking.
C header with register addresses and field information.
HTML website with documentation of registers and fields.
The tool can also be extended by writing your own code generator using a simple but powerful API.
This project is mature and used in many production environments. The maintainers place high focus on quality, with everything having good unit test coverage and a thought-out structure.
Project details
Release history Release notifications | RSS feed
Download files
Download the file for your platform. If you're not sure which to choose, learn more about installing packages.
Source Distribution
Built Distribution
Hashes for hdl_registers-5.1.1-py3-none-any.whl
Algorithm | Hash digest | |
---|---|---|
SHA256 | 77f18d1c821e94c5b8fc4ef255cfbd03abe5c985e0c6cb4531a4dc847beb8b88 |
|
MD5 | 8ea45ada576523b338017426140c16f1 |
|
BLAKE2b-256 | fe6ae70cb122d7d05df0e03932ee40783eae7ab3aa17b58f4c3c75741c7a20a0 |