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hdl synthesis toolkit

Project description

HWToolkit (hwt),

the library for hardware development in Python

Build Status Coverage Status codecov PyPI version Documentation Status Google group Python version Join the chat at https://gitter.im/hwt-community/community ROADMAP

Keywords

  • Metaprogramming (Hardware Construction Language HCL, templatization) + HLS.
  • Simulator API, UVM
  • Buildtool, IP core generator

How HWT can help you?

  • The lower layer (IR, HDL serializers) is a shield against a problems related to VHDL/Verilog. It is checking for correctness and synthetisability and removing specific of HDLs.
  • The system level and HLS layer allows you to quickly build desing generators with advance optimisation techniques of your choice.
  • Simulator API and it's UVM simulation environment is just python object with C++ binding. This makes it easy to use while not sacrificing performance.
  • Rich type system can describe also data locality and packet features. This significantly simplifies configuration of component which are working with packets or any data over remote bus.
  • HWT is not compiler nor transpiler but it is actually a core library. It contains only necessary stuff and you can can modify/extend any part any time. Because the word of HW developement is always full of unexpected situations.

Features

  • Hardware Construction Language (HCL) (example simple, showcase). It is somewhere between HLS and HDL. It offers HLS style of coding but at the same time it allows you to manipulate HDL objects. This means it is a little bit slower to write a prototype than you would in HLS, but you always know what, how and why is happening.
  • Digital circuit simulator with UVM like verification environment (example usage CAM, structWriter_test.py)
  • Tools for static analysis (resourceAnalyzer, example usage cntr_test.py)
  • Serializers to export HWT designs into multiple target HDLs (verilog, VHDL, system-c, IP-core packager, hwt itself...)

HWT uses hilevel-netlists for internal representation of target design. Optimized netlists are generated from usual code statements, function calls, statements etc (hw processes are automatically resolved). This netlist is easy to use and easy to modify or analyse by user if there is something missing in main library. Also serialization modes allows to tweaks how component should behave during serialization.

HWT performs no HLS planing or schedueling. HWT is also good as API for code generating by more advanced tools. Hierarchy of components/interfaces/types is not limited. User specifed names are checked for collision with target language.

HWT designs are instances. No specific exceution is required, just use to_rtl metod or other (take a look at examples).

HWT ecosystem

  • netlistDB - High performance circuit database, C++
  • hwtLib - Library with examples and real designs.
  • sphinx-hwt - Plugin for sphinx documentation generator which adds interactive shematic into html documentation.
  • hdlConvertor - (System) Verilog/VHDL parser
  • hwtHls - High Level Synthetizer (alghorithmic description -> RTL)
  • hwtHdlParsers (not maintained)- (System) Verilog/VHDL compatibility layer at which allows you to import objects from HDL.
  • cocopy - Verilator simulator - Python binding
  • ipCorePackager - IPCore generator (Vivado, Quartus support etc.) automatic specification of interfaces by metaclass description, register map, clk domains etc.
  • pyMathBitPrecise - Bit precise integer types.

Installation

This library is a regular python package. You can install it using:

# system-wide, use -u for local use only
sudo pip3 install hwt

Then you are able to use functions and classes defined in the hwt library from a python console or script. Installation of hwtLib is recomended as it contains common interfaces, agents, components etc...

FAQ

  • Where is the entry point of the compiler?
    • This is not a compiler, it is library of the objects which can be converted to Verilog/VHDL and back.
  • How do I get Verilog/VHDL?
  • How do I define my interface type, protocol and simulation agent?
    • Derive from any Interface class. example
  • I do have c structure of UDP header, how do I send/recieve UDP packet over AXI-stream interface?
    • Define HStruct type composed of eth_header_t, IPv4_header_t and HStream(uint8_t) and use AxisFrameGen. There is and example of ping responder

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Related open-source

Board support libraries (Potential candidates for public integration)

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