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hdl synthesis toolkit

Project description

HWToolkit (hwt),

the library for hardware development in Python

Build Status Coverage Status PyPI version Documentation Status Google group Python version ROADMAP


  • Metaprogramming (Hardware Construction Language HCL, templatization) + HLS.
  • Simulator API, UVM
  • Buildtool, IP core generator

How HWT can help you?

  • The lower layer (IR, HDL serializers) is a shield against a problems related to VHDL/Verilog it is checking for correctness and synthetisability and removing specific of HDLs.
  • Simulator API - UVM simulation environment as a normal python object, easy to use while not sacrificing performance. Python driven.
  • C inspired type system is most important part of HWT as it allows all components use same description and thanks to stream-memory and other component generators significantly simplifies the developement of components which are using complex data structures. The typesystem contains not just struct/union, but also frame templates which can describe spartial data and the creation of the frames from data.
  • KISS (Keep it stupid and simple), each functionality separated as independent, but compatible, library so you do not have to care about it if you are not using it. Learning curve optimisation.


  • Hardware Construction Language (HCL) (example simple, showcase). It is somewhere between HLS and HDL. It offers HLS style of coding but at the same time it allows you to manipulate HDL objects. This means it is a little bit slower to write a prototype than you would in HLS, but you always know what, how and why is happening.
  • Digital circuit simulator with UVM like verification environment (example usage CAM,
  • Tools for static analysis (resourceAnalyzer, example usage
  • Serializers to export HWT designs into multiple target HDLs (verilog, VHDL, system-c, IP-core packager, hwt itself...)

HWT uses hilevel-netlists for internal representation of target design. Optimized netlists are generated from usual code statements, function calls, statements etc (hw processes are automatically resolved). This netlist is easy to use and easy to modify or analyse by user if there is something missing in main library. Also serialization modes allows to tweaks how component should behave during serialization.

HWT performs no HLS planing or schedueling. HWT is also good as API for code generating by more advanced tools. Hierarchy of components/interfaces/types is not limited. User specifed names are checked for collision with target language.

HWT designs are instances. No specific exceution is required, just use toRtl metod or other (take a look at examples).

HWT ecosystem

  • netlistDB - High performance circuit database, C++
  • hwtLib - Library with examples and real designs.
  • sphinx-hwt - Plugin for sphinx documentation generator which adds interactive shematic into html documentation.
  • hdlConvertor - (System) Verilog/VHDL parser
  • hwtHls - High Level Synthetizer (alghorithmic description -> RTL)
  • hwtHdlParsers (not maintained)- (System) Verilog/VHDL compatibility layer at which allows you to import objects from HDL.
  • cocopy - Verilator simulator - Python binding
  • ipCorePackager - IPCore generator (Vivado, Quartus support etc.) automatic specification of interfaces by metaclass description, register map, clk domains etc.
  • pyMathBitPrecise - Bit precise integer types.


This library is a regular python package. You can install it using:

# system-wide, use -u for local use only
sudo pip3 install hwt

Then you are able to use functions and classes defined in the hwt library from a python console or script. Installation of hwtLib is recomended as it contains common interfaces, agents, components etc...


  • Where is the entry point of the compiler?
    • This is not a compiler, it is library of the objects which can be converted to Verilog/VHDL and back.
  • How do I get Verilog/VHDL?
  • How do I define my interface type, protocol and simulation agent?
    • Derive from any Interface class.
  • I do have c structure of UDP header, how do I send/recieve UDP packet over AXI-stream interface?
    • Define HStruct type composed of eth_header_t, IPv4_header_t and HStream(uint8_t) and use AxisFrameGen. There is and example of ping responder

Similar projects

  • autofpga - C++, A utility for Composing FPGA designs from Peripherals
  • chisel - 2012-?, Scala, HCL
  • concat - 2016-?, Haskell, Haskell to hardware
  • DUH - JS, simple convertor between verilog/scala/ipxact
  • edalize - 2018-?, Python, abstraction layer for eda tools
  • garnet -2018-?, Python, Coarse-Grained Reconfigurable Architecture generator based on magma
  • hammer - 2017-?, Python, Highly Agile Masks Made Effortlessly from RTL
  • hoodlum - 2016-?, Rust, HCL
  • ILAng - modeling and verification platform for SoCs where Instruction-Level Abstraction (ILA) is used as the formal model for hardware components.
  • jhdl - ?-2017, C++ Verilog/VHDL -> systemC, prototype
  • Kactus2 - IP-core packager
  • lgraph -
  • magma - 2017-?, Python, HCL
  • migen - 2013-?, Python, HCL
  • mockturtle - logic network library
  • MyHDL - 2004-?, Python, Process based HDL
  • nmigen -
  • percy - Collection of different synthesizers and exact synthesis methods for use in applications such as circuit resynthesis and design exploration.
  • pygears - , Python, function style HDL generator
  • PyMTL3 2018-?
  • PyMTL - 2014-?, Python, Process based HDL
  • PyRTL - 2015-?, Python, HCL
  • Pyverilog - 2013-? Python-based Hardware Design Processing Toolkit for Verilog HDL
  • sail 2018-?, (OCaml, Standard ML, Isabelle) - architecture definition language
  • spatial - Scala, an Argon DSL like, high level abstraction
  • SpinalHDL - 2015-?, Scala, HCL
  • Verilog.jl - 2017-2017, Julia, simple Julia to Verilog transpiler
  • veriloggen - 2015-?, Python, Verilog centric HCL with HLS like features

Related open-source

Board support libraries (Potential candidates for public integration)

  • litex - Buildsystem for migen
  • loam - Buildsystem for magma

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