hdl synthesis toolkit
the library for hardware development in Python
Hardware Description Language (example showcase0.py )
Digital circuit simulator with UVM like verification environment (example usage structWriter_test.py)
Serializers to export HWT designs into multiple target HDLs (multiple standards verilog, VHDL, system-c, IP-core packager, hwt itself...)
Every part of HWT is optional and can be replaced or excluded by user, there are no magic classes. HWT uses netlists for representation of target design. Optimized netlists are generated from usual code statements, function calls etc. HWT performs no HLS planing or schedueling (can be done in hwtHls ) HWT itself is API for code generating by more advanced tools, but it is easy to use it directly.
There is library of examples and real designs as well at hwtLib.
(System) Verilog/VHDL compatibility layer at hwtHdlParsers which allows you to import objects from HDL (not maintained).
There is (System) Verilog/VHDL parser hdlConvertor
There is prototype (pre alfa) of IDE hwtIde
This library is regular python package. You can install it using:
# system-wide sudo pip3 install hwt # or for local use only pip3 install hwt -u
Then you are able to use functions and classes defined in hwt library from python console or script. Installation of hwtLib is recomended.
hwtLib contains abstract class called BusEndpoint. Object from this class uses c-like-structure as description of memory space. The goal is create a memory space decoder for any interface just from c-like structure description. This allows for example to switch design from Avalon or Axi to PCI-e in just one line of code. And also c-structure-like description of memory space is very user friendly and greatly reduces the possible errors in design.
AxiLiteEndpoint is derived from BusEndpoint class and implements slave decoder for AxiLite bus (AxiLiteEndpoint is component which takes c-like-struct and generates address encoder). It is also possible to specify meta in struct description to specify output interface explicitly.
from hwt.synthesizer.utils import toRtl from hwt.serializer.vhdl.serializer import VhdlSerializer from hwt.hdl.types.struct import HStruct from hwtLib.types.ctypes import uint32_t, uint16_t from hwtLib.amba.axiLite_comp.endpoint import AxiLiteEndpoint t = HStruct( (uint32_t, "data0"), # optimized address selection because data are aligned (uint32_t, "data1"), (uint32_t, "data2"), (uint32_t, "data3"), # padding (uint32_t, None), # type can be any type (HStruct( (uint16_t, "data4a"), (uint16_t, "data4b"), (uint32_t, "data4c") ), "data4"), ) u = AxiLiteEndpoint(t) # configuration u.ADDR_WIDTH.set(8) u.DATA_WIDTH.set(32) # convert unit instance to target HDL print(toRtl(u, serializer=VhdlSerializer)) # print interfaces just for demonstration print(u.bus) # decoded interfaces for data type will have same structure as c-struct description (but it is interface) print(u.decoded.data3) print(u.decoded.data4)
Expected output (trimmed):
-- -- Delegate request from AxiLite interface to fields of structure -- write has higher priority -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY AxiLiteEndpoint IS GENERIC (ADDR_WIDTH: INTEGER := 8; DATA_WIDTH: INTEGER := 32; decoded_data0_ADDR_WIDTH: INTEGER := 2; ... ); PORT (bus_ar_addr: IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); bus_ar_ready: OUT STD_LOGIC; bus_ar_valid: IN STD_LOGIC; ... decoded_data0_addr: OUT STD_LOGIC_VECTOR(decoded_data0_ADDR_WIDTH - 1 DOWNTO 0); decoded_data0_din: OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); decoded_data0_dout: IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); decoded_data0_en: OUT STD_LOGIC; decoded_data0_we: OUT STD_LOGIC; ... <AxiLite, name=bus, _masterDir=DIRECTION.OUT> <RegCntrl, name=decoded.data3, _masterDir=DIRECTION.OUT> <StructIntf, name=decoded.data4, _masterDir=DIRECTION.OUT>