hwt 2.7

hdl synthesis toolkit

HWToolkit (hwt),

the library for hardware development in Python

The goals of HWT

• Meta programing + HLS, standard code generators to prevent code duplications.
• Integration with community and commercial tools, flexible lightway user extensible architecture.
• Simple verifications and testing.

Features

• Meta Hardware Description Language (example simple, showcase). It is somewhere between HLS and HDL. It offers HLS style of coding but in same time it allows you to manipulate with HDL objects. It means it is little bit slower to write a prototype than you would in HLS, but you always know what, how and why is happening.
• Digital circuit simulator with UVM like verification environment (example usage CAM, structWriter_test.py)
• Tools for static analysis (resourceAnalyzer, example usage cntr_test.py)
• Serializers to export HWT designs into multiple target HDLs (verilog, VHDL, system-c, IP-core packager, hwt itself...)

HWT uses hilevel-netlists for internal representation of target design. Optimized netlists are generated from usual code statements, function calls, statements etc (hw processes are automatically resolved). This netlist is easy to use and easy to modify or analyse by user if there is something missing in main library. Also serialization modes allows to tweaks how component should behave durning serialization.

HWT performs no HLS planing or schedueling. HWT is also good as API for code generating by more advanced tools. Hierarchy of components/interfaces/types is not limited. User specifed names are checked for collision with target language.

HWT designs are instances. No specific exceution is required, just use toRtl metod or other (take a look at examples).

HWT ecosystem

• hwtLib - Library full of examples and real designs.
• sphinx-hwt - Plugin for sphinx documentation generator which adds shematic into html documentaion.
• hdlConvertor - (System) Verilog/VHDL parser
• hwtHls - High Level Synthetizer (alghorithmic description -> RTL)
• hwtHdlParsers (not maintained)- (System) Verilog/VHDL compatibility layer at which allows you to import objects from HDL.

Installation

This library is regular python package. You can install it using:

# system-wide, use -u for local use only
sudo pip3 install hwt

Then you are able to use functions and classes defined in hwt library from python console or script. Installation of hwtLib is recomended as it contains all interfaces agents etc...

Similar projects

• chisel - 2012-?, Scala, meta HDL
• SpinalHDL - 2015-?, Scala, meta HDL
• migen - 2013-?, Python, meta HDL
• MyHDL - 2004-?, Python, Process based HDL
• PyMTL - 2014-?, Python, Process based HDL
• veriloggen - 2015-?, Python, Verilog centric meta HDL with HLS like features
• hoodlum - 2016-?, Rust, meta HDL
• magma - 2017-?, Python, meta HDL
• garnet -2018-?, Python, Coarse-Grained Reconfigurable Architecture generator based on magma
• concat - 2016-?, Haskell, Haskell to hardware
• PyRTL - 2015-?, Python, meta HDL
• Verilog.jl - 2017-2017, Julia, simple Julia to Verilog transpiler
• Kactus2 - IP-core packager

Related open-source

• vtr-verilog-to-routing
• verilator - Verilog -> C/C++ sim
• yosys - RTL synthesis framework

Board support libraries (Potential candidates for public integration)

• loam - Buildsystem for magma
• litex - Buildsystem for migen