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Scriptable universal IP-core generator

Project description

ipCorePackager

Build Status Coverage Status PyPI version Documentation Status Python version

Scriptable universal IP-Core generator

Export formats

  • IP-XACT (Vivado)
  • Quartus (QSys) *_hw.tcl

What is IP-Core packager.

IP-Core packager is a tool which generates component.xml or _hw.tcl files which are description of interface of hardware design usually written in Verilog or VHDL. Result is the package with HDL (Verilog/VHDL) files, constraints files (XDC, UCF, ...) tcl based GUI and package description file. IP-Core packages greatly simplifies integration of hardware projects, all major synthesis tools (Xilinx Vivado, Intel Quartus, ...) are supporting them directly and for rest it is better to have IP-Core because of consystency.

How to use IpCorePackager

IpCorePackager is API for generating of IP-XACT and _hw.tcl files. In order to use the IpCorePackager you need two things.

  • You need to have definitions of Interface IP-Core meta for interfaces which require some special care (require to define some parameter in IP-Core, etc.), This meta has to be subclass of ipCorePackager.intfIpMeta.IntfIpMeta

  • You need to define methods in ipCorePackager.packager.IpCorePackager which are raising the NotImplementedError. This methods are because ipCorePackager does not dependeds on reprenation of design.

This library is used by hwt there you can find reference implementation of IpCorePackager methods for hwt style hardware description.

The hwtLib library contains definitions of IntfIpMeta descriptions for common interfaces.

Similar projects

  • Kactus2 - IP-core packager
  • Qgen - Quartus ip core packager for MyHDL

Project details


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ipCorePackager-0.2.tar.gz (15.2 kB) Copy SHA256 hash SHA256 Source None

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