Design flow integration and automation with Magia

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  • License: MIT License, Other/Proprietary License (LICENSE)
  • Author: khwong-c64
  • Tags Verilog HDL, SystemVerilog, Synthesizable, RTL, HDL, Hardware Description Language, Code Generation, FPGA, ASIC, EDA, RTL Design
  • Requires: Python <4.0, >=3.10
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Project description

Magia Flow

Brief

Design flow integration and automation with Magia.

Project Roadmap

TBD

Installation

pip install magia-flow

Examples

TBD

Documentation

TBD

Contributing

We also have a Contribution Guideline and Code of Conduct. Please take a look before you contribute.

In case you are interested in this project, contact me via: https://github.com/khwong-c

Reference

TBD

Project details

Verified details

These details have been verified by PyPI
Maintainers
Avatar for khwong-c from gravatar.com khwong-c

Unverified details

These details have not been verified by PyPI
Project links
Meta
  • License: MIT License, Other/Proprietary License (LICENSE)
  • Author: khwong-c64
  • Tags Verilog HDL, SystemVerilog, Synthesizable, RTL, HDL, Hardware Description Language, Code Generation, FPGA, ASIC, EDA, RTL Design
  • Requires: Python <4.0, >=3.10
Classifiers

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This version

0.2.1

0.2.0

0.1.0

0.0.1

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