A Tool for HDL-based Synthesis of Reversible Circuits

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Project description

[!NOTE] This project is currently in low maintenance mode. We will still fix bugs and accept pull requests, but we will not actively develop new features.

SyReC Synthesizer: A Tool for HDL-based Synthesis of Reversible Circuits

A tool for HDL-based synthesis of reversible circuits developed as part of the Munich Quantum Toolkit (MQT) by the Chair for Design Automation at the Technical University of Munich. It builds upon MQT Core, which forms the backbone of the MQT.

If you have any questions, feel free to contact us by creating an issue on GitHub.

Getting Started

The SyReC Synthesizer is available via PyPI for Linux, macOS, and Windows.

In order to make the library as easy to use as possible (without compilation), we provide pre-built wheels for most common platforms (64-bit Linux, MacOS, Windows). These can be installed using
```
(venv) $ pip install mqt.syrec
```
Once installed, start the SyReC Synthesizer GUI by running:
```
(venv) $ syrec-editor
```

Detailed documentation on all available methods, options, and input formats is available at ReadTheDocs.

System Requirements and Building

The implementation is compatible with any C++17 compiler and a minimum CMake version of 3.19. Please refer to the documentation on how to build the project.

Building (and running) is continuously tested under Linux, macOS, and Windows using the latest available system versions for GitHub Actions.

References

SyReC Synthesizer has been developed based on methods proposed in the following papers:

[1] S. Adarsh, L. Burgholzer, T. Manjunath and R. Wille. SyReC Synthesizer: An MQT tool for synthesis of reversible circuits. Software Impacts, 2022.

[2] R. Wille, S. Offermann, and R. Drechsler. SyReC: A Programming Language for Synthesis of Reversible Circuits. In Forum on Specification and Design Languages (FDL), 2010.

[3] R. Wille, E. Schönborn, M. Soeken, and R. Drechsler. SyReC: A hardware description language for the specification and synthesis of reversible circuits. Integration (The VLSI Journal), 2016.

[4] R. Wille, M. Haghparast, S. Adarsh, and T. Manjunath. Towards HDL-based Synthesis of Reversible Circuits with No Additional Lines. In International Conference on Computer Aided Design (ICCAD), 2019.

Project details

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Release history Release notifications | RSS feed

This version

1.1.2

Jan 2, 2024

1.1.1

Dec 12, 2023

1.1.0

Sep 29, 2023

1.0.1

Jun 14, 2023

1.0.0

Oct 29, 2022

0.2.0

Sep 5, 2022

0.1.0

Apr 22, 2022

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SHA256	`a0f32554f851ded0263e729555f6f6fc71555c3e4c62371129a4204587c28fae`
MD5	`6e37244161fe9b20e8060d1126922883`
BLAKE2b-256	`8f70acd7db15793b317da50306b62c14ff19f70ba9fb16c2de6eae78a9ab2d3b`