Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
Project description
PeakRDL-BusDecoder
Generate a SystemVerilog bus decoder from SystemRDL that splits CPU interface signals to multiple sub-address spaces. This tool is designed for creating hierarchical register address maps by decoding bus transactions and routing them to the appropriate child address maps.
For the command line tool, see the PeakRDL project.
Documentation
See the PeakRDL-BusDecoder Documentation for more details
Release history Release notifications | RSS feed
Download files
Download the file for your platform. If you're not sure which to choose, learn more about installing packages.
Source Distribution
Built Distribution
Filter files by name, interpreter, ABI, and platform.
If you're not sure about the file name format, learn more about wheel file names.
Copy a direct link to the current filters
File details
Details for the file peakrdl_busdecoder-0.2.0.tar.gz.
File metadata
- Download URL: peakrdl_busdecoder-0.2.0.tar.gz
- Upload date:
- Size: 617.2 kB
- Tags: Source
- Uploaded using Trusted Publishing? No
- Uploaded via: uv/0.9.5
File hashes
| Algorithm | Hash digest | |
|---|---|---|
| SHA256 |
d67839404a1a5025c2d7f7462ff7d7b5ab846fb18bd42347a4e88c566acc3312
|
|
| MD5 |
0feb268ceeec9e97db35459ad83c20e4
|
|
| BLAKE2b-256 |
b0a7bc6ba752677da69efc432c9b7e8fab2c34b77b75c9480727aa233030cf2e
|
File details
Details for the file peakrdl_busdecoder-0.2.0-py3-none-any.whl.
File metadata
- Download URL: peakrdl_busdecoder-0.2.0-py3-none-any.whl
- Upload date:
- Size: 41.7 kB
- Tags: Python 3
- Uploaded using Trusted Publishing? No
- Uploaded via: uv/0.9.5
File hashes
| Algorithm | Hash digest | |
|---|---|---|
| SHA256 |
27f0067903f319404549d79a6708c8d10843ffb8ad993808847e885f7d76cd96
|
|
| MD5 |
74520fead77da5a97f56f21cd39ae81b
|
|
| BLAKE2b-256 |
dfd186b1a55d28ec5a8d5d3e19d0908a2511714b394a25d8bee1d784ee905ad3
|
