Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
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PeakRDL-BusDecoder
Generate a SystemVerilog bus decoder from SystemRDL that splits CPU interface signals to multiple sub-address spaces. This tool is designed for creating hierarchical register address maps by decoding bus transactions and routing them to the appropriate child address maps.
For the command line tool, see the PeakRDL project.
Documentation
See the PeakRDL-BusDecoder Documentation for more details
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