Compile SystemRDL into a SystemVerilog control/status register (CSR) block

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License: GNU General Public License v3 (GPLv3)

Author: Alex Mykyta

Requires: Python >=3.6

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Project description

Documentation Status build PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block

Documentation

See the PeakRDL-regblock Documentation for more details

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License: GNU General Public License v3 (GPLv3)

Author: Alex Mykyta

Requires: Python >=3.6

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0.22.0

0.21.0

0.20.0

0.19.0

0.18.0

0.17.0

0.16.0

0.15.0

0.14.0

0.13.0

0.12.0

0.11.0

0.10.0

0.9.0

0.8.0

0.7.0

0.6.0

This version

0.5.0

0.4.0

0.3.0

0.2.0

0.1.0a1 pre-release

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peakrdl-regblock-0.5.0.tar.gz (41.1 kB view hashes)

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