PeakRDL-verilog
Generate Verilog register model from compiled SystemRDL input
Installing
Install from github only at the moment.
Exporter Usage
Pass the elaborated output of the SystemRDL Compiler to the exporter.
import sys
from systemrdl import RDLCompiler, RDLCompileError
from peakrdl.verilog import VerilogExporter
rdlc = RDLCompiler()
try:
rdlc.compile_file("path/to/my.rdl")
root = rdlc.elaborate()
except RDLCompileError:
sys.exit(1)
exporter = VerilogExporter()
exporter.export(root, "test.sv")
Verification
The tool will generate a tb for your module in the same directory. This will test the HW interface
Reference
VerilogExporter(**kwargs)
Constructor for the Verilog Exporter class
Optional Parameters
user_template_dir- Path to a directory where user-defined template overrides are stored.
user_template_context- Additional context variables to load into the template namespace.
VerilogExporter.export(node, path, **kwargs)
Perform the export!
Parameters
node- Top-level node to export. Can be the top-level
RootNodeor any internalAddrmapNode.
- Top-level node to export. Can be the top-level
path- Output file.
Optional Parameters
1 maintainer
Metadata
1 maintainer
Release files for peakrdl-verilog 1.0.0
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| File | Size | Uploaded | Provenance | Actions |
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| peakrdl_verilog-1.0.0-py3.10.egg | Legacy Egg format | - | - | Details for peakrdl_verilog-1.0.0-py3.10.egg |
Total release size: 55.4 kB
Release files / peakrdl-verilog-1.0.0.tar.gz
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| Size | 26.8 kB |
| Tags | Egg |
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