An abstract model of EDA tool projects.
Project description
Main Goals
This package provides a unified abstract project model for HDL designs and EDA tools. Third-party frameworks can derive own classes and implement additional logic to create a concrete project model for their tools.
Frameworks consuming this model can build higher level features and services on top of such a model, while supporting multiple input sources.
Data Model
- The toplevel element is a
Project
, which contains one or multiple designs. - A
Design
is a variant of a project and contains filesets. - A
FileSet
contains files or further sub-filesets. - A
File
represents a single file. E.g. source files, configuration files, constraint files. - A
VHDLLibrary
represents a group ofVHDLSourceFile
s being compiled into the same VHDL library.
Features
-
Construct a project model:
- top-down (project → design → fileset → file) or
- bottom-up (file → fileset → design → project) or
- parsing a project file.
-
Designs, filesets and files can use absolute or relative paths.
ResolvedPath
returns the resolved absolute path to an object.
-
Projects, designs, filesets and files can be validated (e.g. if the path exists).
-
Projects, designs, filesets and files can have user-defined attributes.
- User-defined attributes are resolved bottom-up.
Project File Readers
OSVVM *.pro
File Reader
ProjectModel can read *.pro
files and extract source files. Included *.pro
files
are represented as sub-filesets.
Xilinx Vivado *.xpr
Reader
ProjectModel can read *.xpr
files and extract source, constraint and simulation
files while preserving the fileset structure.
Use Cases
- Reading OSVVM's
*.pro
files. - Reading Xilinx Vivado's
*.xpr
files.
Examples
from pathlib import Path
from pyEDAA.ProjectModel import Project, Design, FileSet, VHDLSourceFile
print(f"Current working directory: {Path.cwd()}")
projectDirectory = Path.cwd() / "../project"
print(f"Project directory: {projectDirectory!s} - {projectDirectory.exists()}")
project = Project("myProject", rootDirectory=projectDirectory)
designA = Design("designA", project=project, directory=Path("designA"))
designAFileset = FileSet("srcA", design=designA)
for vhdlFilePath in designAFileset.ResolvedPath.glob("*.vhdl"):
designAFileset.AddFile(VHDLSourceFile(vhdlFilePath))
libFileset = FileSet("lib", Path("../lib"), design=designA)
for vhdlFilePath in libFileset.ResolvedPath.glob("*.vhdl"):
libFileset.AddFile(VHDLSourceFile(vhdlFilePath))
print(f"All VHDL files in {designA.Name}:")
for file in designA.Files(fileType=VHDLSourceFile):
print(f" {file.Path}")
Consumers
This layer is used by:
- 🚧 pyEDAA.Workflow
References
- Paebbels/pyIPCMI: pyIPCMI/Base/Project.py
- VUnit/vunit: vunit/project.py
- PyFPGA/pyfpga: fpga/project.py
- olofk/fusesoc: fusesoc/capi2/core.py
- XedaHQ/xeda: xeda/flows/flow.py
- tsfpga/tsfpga: tsfpga/build_project_list.py
- hdl-make: hdlmake/
- OSVVM/OSVVM-Scripts: OsvvmProjectScripts.tcl
Contributors
- Patrick Lehmann (Maintainer)
- Unai Martinez-Corral
- Stefan Unrein
- and more...
License
This Python package (source code) licensed under Apache License 2.0.
The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).
SPDX-License-Identifier: Apache-2.0
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