An abstract SystemVerilog language model (incl. Verilog).
Project description
An abstract language model of SystemVerilog (incl. Verilog) written in Python.
Main Goals
This package provides a unified abstract language model for SystemVerilog (incl. Verilog). Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.
Projects consuming pre-processed System Verilog data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.
Use Cases
pySVModel Generators
TBD
pySVModel Consumers
TBD
Examples
List all Modules with Parameters and Ports
TBD
Contributors
- Patrick Lehmann (Maintainer)
- Unai Martinez-Corral
- and more...
License
This Python package (source code) licensed under Apache License 2.0.
The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).
SPDX-License-Identifier: Apache-2.0
Project details
Download files
Download the file for your platform. If you're not sure which to choose, learn more about installing packages.
Source Distribution
Built Distribution
Hashes for pySVModel-0.3.1-py3-none-any.whl
Algorithm | Hash digest | |
---|---|---|
SHA256 | 1ba7758e1c399fa58e3507be4e95f0b4218d440c751c75fde84a62362b2ff946 |
|
MD5 | b8d92a58b571c7afd3b102db98c8c213 |
|
BLAKE2b-256 | ef42b923e6ad2f8d11b3ee9b3fe697077dc933858ca018fc81a6195bf8b69c7b |