An abstract SystemVerilog language model (incl. Verilog).
Project description
An abstract language model of SystemVerilog (incl. Verilog) written in Python.
Main Goals
This package provides a unified abstract language model for SystemVerilog (incl. Verilog). Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.
Projects consuming pre-processed System Verilog data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.
Use Cases
pySVModel Generators
TBD
pySVModel Consumers
TBD
Examples
List all Modules with Parameters and Ports
TBD
Contributors
- Patrick Lehmann (Maintainer)
- Unai Martinez-Corral
- and more...
License
This Python package (source code) licensed under Apache License 2.0.
The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).
SPDX-License-Identifier: Apache-2.0
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