Skip to main content

An abstract VHDL language model.

Project description

Sourcecode on GitHub Sourcecode License GitHub tag (latest SemVer incl. pre-release) GitHub release (latest SemVer incl. including pre-releases) GitHub release date Dependent repos (via libraries.io)
GitHub Workflow - Build and Test Status Codacy - Quality Codacy - Coverage Codecov - Branch Coverage Libraries.io SourceRank
GitHub Workflow Release Status PyPI PyPI - Status PyPI - Python Version Libraries.io status for latest release Requires.io
GitHub Workflow - Documentation Status Documentation License Documentation - Read Now!

pyVHDLModel

An abstract VHDL language model written in Python.

Main Goals

This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.

Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.

Use Cases

pyVHDLModel Generators

  • High-level API for GHDL's libghdl offered via pyghdl.
  • Code Document-Object-Model (Code-DOM) in pyVHDLParser.

pyVHDLModel Consumers

  • Create graphical views of VHDL files or designs.
    Possible candidates: Symbolator
  • Created a (re)formatted output of VHDL.

Examples

List all Entities with Generics and Ports

The following tiny example is based on GHDL's pyGHDL.dom package implementing pyVHDLModel.

from pathlib import Path
from pyGHDL.dom.NonStandard import Design, Document

sourceFile = Path("example.vhdl")

design = Design()
library = Design.GetLibrary("lib")
document = Document(sourceFile)
design.AddDocument(document, library)

for entity in document.Entities:
  print("{}".format(entity.Name))
  print("  generics:")
  for generic in entity.Generics:
    print("  - {} : {!s} {}".format(
      generic.Name, generic.Mode, generic.SubTypeIndication)
    )
  print("  ports:")
  for port in entity.Ports:
    print("  - {} : {!s} {}".format(
      port.Name, port.Mode, port.SubTypeIndication)
    )

Contributors

License

This Python package (source code) licensed under Apache License 2.0.
The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).


SPDX-License-Identifier: Apache-2.0

Project details


Download files

Download the file for your platform. If you're not sure which to choose, learn more about installing packages.

Source Distribution

pyVHDLModel-0.10.5.tar.gz (20.2 kB view hashes)

Uploaded Source

Built Distribution

pyVHDLModel-0.10.5-py3-none-any.whl (18.1 kB view hashes)

Uploaded Python 3

Supported by

AWS AWS Cloud computing and Security Sponsor Datadog Datadog Monitoring Fastly Fastly CDN Google Google Download Analytics Microsoft Microsoft PSF Sponsor Pingdom Pingdom Monitoring Sentry Sentry Error logging StatusPage StatusPage Status page