An abstract VHDL language model.
Project description
pyVHDLModel
An abstract VHDL language model written in Python.
Main Goals
This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.
Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.
Use Cases
pyVHDLModel Generators
- High-level API for GHDL's
libghdl
offered viapyghdl
. - Code Document-Object-Model (Code-DOM) in pyVHDLParser.
pyVHDLModel Consumers
- Create graphical views of VHDL files or designs.
Possible candidates: Symbolator - Created a (re)formatted output of VHDL.
License
This Python package (source code) is licensed under Apache License 2.0.
SPDX-License-Identifier: Apache-2.0
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pyVHDLModel-0.7.5.tar.gz
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