python2verilog 0.2.0

Converts a subset of python generator functions into synthesizable sequential SystemVerilog

python2verilog

• This tool facilitates the conversion of select Python functions into synthesizable sequential SystemVerilog code
• Testbenchs can be automatically generated if the user uses the function within their Python code or provides explicit test cases
• Ideal for quickly translating "CPU code" into hardware descriptions for use on FPGAs, without having to interface with a CPU

from python2verilog import verilogify, Modes

@verilogify(mode=Modes.WRITE)
def hrange(base, limit, step):
    i = base
    while i < limit:
        yield i
        i += step
hrange(10)

Specifications

Constrains on Python functions include:

• Supports only if and while blocks
• Supports only signed integral input/output and operations
• Must be a generator function
• Must be a pure function

Unsupported Python paradigms include but are not limited to the following:

• Regular functions that use the return keyword, instead yield once
• for loops, instead rewrite as a while loop
• Global (nonlocal) variables, instead declare them within the function with minimal overhead
• Keyword arguments, instead use positional arguments
• Function calls, instead use the decorator on each of the subfunctions and manually connect together

Usage and Installation

Try it in Google Collab or check out examples/!

python3 -m pip install --upgrade pip

python3 -m pip install python2verilog

Tested Generations

The Github Actions run all the tests with writing enabled. You may find its output as a Github Artifact availible for download.

For Developers

To setup pre-commit, run pre-commit install.

Github Issues is used for tracking. Milestones and labels are used for milestones and labels respectively.

Docs

Sphinx is used. Follow the Github workflow to generate a local copy.

Testing

Requirements

For most up-to-date information, refer to the pytest github workflow.

A Ubuntu environment (WSL2 works too, make sure to have the repo on the Ubuntu partition, as os.mkfifo is used to avoid writing to disk)

Install required python libraries with python3 -m pip install -r tests/requirements.txt

For automatic Verilog simulation and testing, install Icarus Verilog and its dependencies with sudo apt-get install iverilog expected (uses the unbuffer in expected).

The online simulator EDA Playground can be used as a subsitute if you manually copy-paste the module and testbench files to it.

Creating New Test

To create a new test case and set up configs, run python3 tests/integration/new_test_case.py <test-name>.

Running Tests

To run tests, use python3 -m pytest -sv.

Additional CLI flags can be found in tests/conftest.py.

Use git clean -dxf to remove gitignored and generated files.