python2verilog 0.4.1

Converts a subset of python generator functions into synthesizable sequential SystemVerilog

python2verilog

• This tool facilitates the conversion of select Python generator functions into synthesizable sequential SystemVerilog
• Ideal for quickly translating higher-level "CPU code" into hardware descriptions for use on FPGAs, without needing to interface with or including a CPU in the design
• Testbenches can be automatically generated if the user uses the function within their Python code or provides explicit test cases

from python2verilog import verilogify

@verilogify
def hrange(base, limit, step):
    i = base
    while i < limit:
        yield i
        i += step
print(list(hrange(0, 10, 3)))

Specifications

Constrains on Python functions include:

• Supports only if and while blocks
• Supports only signed integral input/output and operations
• Must be a generator function
• Must be a pure function

Unsupported Python paradigms include but are not limited to the following:

• Regular functions that use the return keyword, instead yield once
• for loops, instead rewrite as a while loop
• Global (nonlocal) variables, instead declare them within the function with minimal overhead
• Keyword arguments, instead use positional arguments
• Function calls, instead use the decorator on each of the subfunctions and manually connect together

Usage and Installation

Try it in Google Collab or check out examples/!

python3 -m pip install --upgrade pip

python3 -m pip install python2verilog

Tested Generations

You may find the output of the integration testing as a Github Artifact available for download.

For Developers

To setup pre-commit, run pre-commit install.

Github Issues are used for tracking.

Sphinx is used for the docs. Follow the sphinx workflow to generate a local copy.

Testing

Requirements

For most up-to-date information, refer to the pytest workflow or the packaging workflow.

A Ubuntu environment (WSL2 works too, make sure to have the repo on the Ubuntu partition, as os.mkfifo is used to avoid writing to disk)

Install required python libraries with python3 -m pip install -r tests/requirements.txt

For automatic Verilog simulation and testing, install Icarus Verilog and its dependencies with sudo apt-get install iverilog expected (uses the unbuffer in expected).

The online simulator EDA Playground can be used as a subsitute if you manually copy-paste the module and testbench files to it.

Running Tests

To run tests, use python3 -m pytest.

CLI arguments for test configuration can be found in tests/conftest.py.

Use git clean -dxf to remove gitignored and generated files.