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Pyverilog-based verification/design tools

Project Description

Introduction

Pyverilog_toolbox is Pyverilog-based verification/design tool.

Accerating your digital circuit design verification.

Thanks to Pyverilog developer shtaxxx.

Software Requirements

Installation

If you want to use Pyverilog as a general library, you can install on your environment by using setup.py.

If you use Python 2.7,

python setup.py install

Or you can use pip

pip install pyverilog_toolbox

Python 3.x is not tried by author.

Tools

codeclone_finder

codeclone_finder can find pair of the register clone, which always hold same value. Also can find pair of the invert register, which always hold different value.

Click here to know usage

combloop_finder

Combinational logic loop is sticky problem, but you can find it by combloop_finder easily.

Click here to know usage

unreferenced_finder

Unreferenced_finder can find signals which isn’t referenced by any signals. By using this, you can delte unnecessary codes.

Click here to know usage

regmap_analyzer

regmap_analyzer can analyze register map structure from RTL. After install Pyverilog_toolbox, you can use regmap analyzer by this command.

Click here to know usage

cnt_analyzer

cnt_analyzer analyze counter property(up or down, max value, reset value and counter dependency). And extracting event which depends on counter value. This feature help you finding redundunt counter, deadlock loop, and other counter trouble.

Click here to know usage

License

Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)

Release History

Release History

History Node

0.0.5

History Node

0.0.4

History Node

0.0.3

History Node

0.0.2

History Node

0.0.1

This version
History Node

0.0.0

Download Files

Download Files

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File Name & Checksum SHA256 Checksum Help Version File Type Upload Date
pyverilog_toolbox-0.0.0.zip (236.2 kB) Copy SHA256 Checksum SHA256 Source Jul 6, 2015

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