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Pyverilog-based verification/design tools

Project description


Pyverilog_toolbox is Pyverilog-based verification/design tool.

Accerating your digital circuit design verification.

Thanks to Pyverilog developer shtaxxx.

Software Requirements


If you want to use Pyverilog as a general library, you can install on your environment by using

If you use Python 2.7,

python install

Or you can use pip

pip install pyverilog_toolbox

Python 3.x is not tried by author.



codeclone_finder can find pair of the register clone, which always hold same value. Also can find pair of the invert register, which always hold different value.

Click here to know usage


Combinational logic loop is sticky problem, but you can find it by combloop_finder easily.

Click here to know usage


Unreferenced_finder can find signals which isn’t referenced by any signals. By using this, you can delte unnecessary codes.

Click here to know usage


regmap_analyzer can analyze register map structure from RTL. After install Pyverilog_toolbox, you can use regmap analyzer by this command.

Click here to know usage


cnt_analyzer analyze counter property(up or down, max value, reset value and counter dependency). And extracting event which depends on counter value. This feature help you finding redundunt counter, deadlock loop, and other counter trouble.

Click here to know usage


Apache License 2.0 (

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