Pyverilog-based verification/design tools
Pyverilog_toolbox is Pyverilog-based verification/design tool.
Accerating your digital circuit design verification.
Thanks to Pyverilog developer shtaxxx.
- Python (2.7)
- Pyverilog (you can download from https://github.com/shtaxxx/Pyverilog)
If you want to use Pyverilog as a general library, you can install on your environment by using setup.py.
If you use Python 2.7,
python setup.py install
Or you can use pip
pip install pyverilog_toolbox
Python 3.x is not tried by author.
codeclone_finder can find pair of the register clone, which always hold same value. Also can find pair of the invert register, which always hold different value.
Combinational logic loop is sticky problem, but you can find it by combloop_finder easily.
Unreferenced_finder can find signals which isn’t referenced by any signals. By using this, you can delte unnecessary codes.
regmap_analyzer can analyze register map structure from RTL. After install Pyverilog_toolbox, you can use regmap analyzer by this command.
cnt_analyzer analyze counter property(up or down, max value, reset value and counter dependency). And extracting event which depends on counter value. This feature help you finding redundunt counter, deadlock loop, and other counter trouble.
Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)
Copyright (C) 2015, Ryosuke Fukatani