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Pyverilog-based verification/design tools

Project Description


Pyverilog_toolbox is Pyverilog-based verification/design tool including code clone finder, metrics calculator and so on. Pyverilog_toolbox accerating your digital circuit design verification. Thanks to Pyverilog developer shtaxxx.

Software Requirements


(If you want to use GUI stand alone version for windows, Click here to get detail

If you want to use Pyverilog as a general library, you can install on your environment by using

If you use Python 2.7,

python install

Or you can use pip

pip install pyverilog_toolbox

Python 3.x is not tried by author.



codeclone_finder can find pair of the register clone, which always hold same value. Also can find pair of the invert register, which always hold different value.

Click here to get detail


Combinational logic loop is sticky problem, but you can find it by combloop_finder easily.

Click here to get detail


Unreferenced_finder can find signals which isn’t referenced by any signals. By using this, you can delte unnecessary codes.

Click here to get detail


metrics_analyzer is metrics measurment tools for Verilog HDL. You can visualize complecity of module/register/function/.

Click here to get detail


regmap_analyzer can analyze register map structure from RTL.

Click here to get detail


cnt_analyzer analyze counter property(up or down, max value, reset value and counter dependency). And extracting event which depends on counter value. This feature help you finding redundunt counter, deadlock loop, and other counter trouble.

Click here to get detail


Apache License 2.0 (

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Filename, Size & Hash SHA256 Hash Help File Type Python Version Upload Date
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Source None Aug 5, 2015

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