A Python package for textually describing electronic circuit schematics.
SKiDL is a module that allows you to compactly describe the interconnection of electronic circuits and components using Python. The resulting Python program performs electrical rules checking for common mistakes and outputs a netlist that serves as input to a PCB layout tool.
- Free software: MIT license
- Documentation: http://xesscorp.github.io/skidl
- Has a powerful, flexible syntax (because it is Python).
- Permits compact descriptions of electronic circuits (think about not tracing signals through a multi-page schematic).
- Allows textual descriptions of electronic circuits (think about using diff and git for circuits).
- Performs electrical rules checking (ERC) for common mistakes (e.g., unconnected device I/O pins).
- Supports linear / hierarchical / mixed descriptions of electronic designs.
- Fosters design reuse (think about using PyPi and Github to distribute electronic designs).
- Makes possible the creation of smart circuit modules whose behavior / structure are changed parametrically (think about filters whose component values are automatically adjusted based on your desired cutoff frequency).
- Can work with any ECAD tool (only two methods are needed: one for reading the part libraries and another for outputing the correct netlist format).
- Can perform SPICE simulations (Python 3 only).
- Takes advantage of all the benefits of the Python ecosystem (because it is Python).
As a very simple example (and you can see more examples in the SKiDL blog), the SKiDL program below describes a circuit that takes an input voltage, divides it by three, and outputs it:
from skidl import * # Create input & output voltages and ground reference. vin, vout, gnd = Net('VI'), Net('VO'), Net('GND') # Create two resistors. r1, r2 = 2 * Part('device', 'R', TEMPLATE, footprint='Resistors_SMD:R_0805') r1.value = '1K' # Set upper resistor value. r2.value = '500' # Set lower resistor value. # Connect the nets and resistors. vin += r1 # Connect the input to the upper resistor. gnd += r2 # Connect the lower resistor to ground. vout += r1, r2 # Output comes from the connection of the two resistors. generate_netlist()
And this is the output that can be fed to a program like KiCad’s PCBNEW to create the physical PCB:
(export (version D) (design (source "C:\xesscorp\KiCad\tools\skidl\tests\vdiv.py") (date "09/14/2018 08:49 PM") (tool "SKiDL (0.0.23)")) (components (comp (ref R1) (value 1K) (footprint Resistors_SMD:R_0805) (fields (field (name description) Resistor) (field (name keywords) "r res resistor")) (libsource (lib device) (part R)) (sheetpath (names /top/12995167876889795071) (tstamps /top/12995167876889795071))) (comp (ref R2) (value 500) (footprint Resistors_SMD:R_0805) (fields (field (name description) Resistor) (field (name keywords) "r res resistor")) (libsource (lib device) (part R)) (sheetpath (names /top/8869138953290924483) (tstamps /top/8869138953290924483)))) (nets (net (code 0) (name GND) (node (ref R2) (pin 2))) (net (code 1) (name VI) (node (ref R1) (pin 1))) (net (code 2) (name VO) (node (ref R1) (pin 2)) (node (ref R2) (pin 1)))) )
- Fixed an error where creating a backup part library for a design would create extra pins attached to the nets.
- Added Network objects to make it easy to create serial & parallel combinations of two-pin parts.
- SKiDL design hierarchy is now embedded in the KiCad netlist that’s generated.
- Added Interface objects for storing complicated sets of I/O signals for subsystems.
- ERC no longer redundantly checks every segment of a multi-segment net and reports multiple errors.
- copy() function of Part, Bus, Pin, Net objects now returns a scalar object while copy(1) returns a list with one object.
- Bus, Pin, and Net objects now have iterators.
- Corrected initialization of KiCad library search paths.
- Added pull() and fetch() methods for getting/creating existing/new Net and Bus objects.
- Added drive property to pins to override their default pin function attribute.
- Part pins and units can now be accessed as attributes.
- Nets, pins, and buses now support the width property.
- Indexing with brackets now works equivalently for pins, nets, and buses.
- Grouped part pins (such as address and data buses) can now be accessed using a slice-like notation, e.g. memory[‘ADDR[0:7]’].
- Matching of pin lists now begins with normal string matching before using regexes.
- Added more tests and fixed existing tests.
- Selecting part pins now looks for exact match before falling back to regex matching.
- PySpice now needs to be manually installed to perform SPICE simulations.
- SPICE simulations of subcircuits (.SUBCKT) now supported.
- Improvements/additions to the library of supported SPICE parts.
- SPICE simulations of circuits now supported (Python 3 only).
- Modularized code into separate files.
- Parsing of KiCad EESchema libraries made more robust.
- DEFAULT_TOOL replaced with set_default_tool() function.
- Some code simplification by using a context manager for opening files.
- Testing made more robust.
- KiCad netlists are now parsed using the external package kinparse.
- Cleaned-up pylint-identified issues.
- Removed absolute file paths to libraries from tests.
- Fixed problem where the search function was only returning parts found in the last library searched.
- Use of builtin now works with Python 2 & 3.
- Started using namedtuple in some places (like net traversal) for clarity.
- Corrected pin-to-pin connections so if a net is created, it goes into the same Circuit the pins are members of.
- Part templates can now contain a reference to a Circuit object that will be applied when the template is instantiated.
- When pins are connected to nets, or nets to nets, the resulting set of connected nets are all given the same name.
- Buses are not added to a Circuit object if they are already members of it. This fix caused the next problem.
- Buses weren’t getting added to the Circuit object because they already contained a reference to the Circuit. Fixed by clearing ref before adding to Circuit.
- Created mini_reset() method to clear circuitry without clearing library cache so the libraries don’t have to be loaded again (slow).
- search() utility now prints the names of libraries as they are searched so user sees progress.
- Fixed exceptions if part definition contained non-unicode stuff.
- Hide exceptions that occur when using the show() utility.
- More tests added for NC nets and hand-crafted parts.
- default_circuit and the NC net for the active circuit are now made accessible in all modules using __builtin__.
- Corrected error messages that referenced wrong/non-existing variable.
- Inserted NO_LIB for the library if it doesn’t exist when generating KiCad netlists or XML.
- Attributes can now be passed when creating a Circuit object.
- Pins are now associated with part when added to the part.
- Minimum and maximum pins for a part are now computed as needed.
- Each Circuit object now has its own NC net.
- Added tests for bus movement and copying.
- Implemented bus movement between Circuit objects.
- Additional test cases were created.
- Nets and Parts can now be removed from Circuits.
- The circuit that pins and nets are in is now checked before connections are made so cross-circuit connections are not created.
- Default members were added to Pin and Part objects so they would always exist and not cause errors when missing.
- Implemented moving Parts and Nets from one circuit to another (almost).
- Nets with no attached pins are now added to a circuit.
- Re-wrote some tests to account for the presence of no-pin nets in a circuit.
- A class method was missing its ‘self’ argument.
- Fixed @subcircuit decorator so it won’t cause an error if the function it decorates doesn’t have a ‘circuit’ keyword argument.
- Split the unit tests across multiple files. Added setup/teardown code.
- Added capability to create multiple, independent Circuit objects to which Parts and Nets can be assigned. The default circuit is still the target if not Circuit is explicitly referenced.
- Added IOError to exception list for opening a SKiDL part library.
- Part libraries in SKiDL format are now supported.
- Parts can now be created on-the-fly and instantiated or added to libraries.
- The parts used in a circuit can be stored in a backup SKiDL library and used if the original libraries are missing.
- The KiCad standard part libraries were converted to SKiDL libraries and placed in skidl.libs.
- Nets without pins can now be merged.
- Parts and Pins are now sorted when netlists are generated.
- For an existing Bus, new bus lines can be inserted at any position or the bus can be extended.
- Use getattr() instead of __class__.__dict__ so that subclasses of SKiDL objects can find attributes named within strings without searching the __mor__.
- skidl_to_netlist now uses templates.
- Default operation of search() is now less exacting.
- Traceback is now suppressed if show() is passed a part name not in a library.
- Lack of KISYSMOD environment variable no longer causes an exception.
- requirements.txt file now references the requirements from setup.py.
- Changed setup so it generates a pckg_info file with version, author, email.
- Fixed error caused when trying to find script name when SKiDL is run in interactive mode.
- Silenced errors/warnings when loading KiCad part description (.dcm) files.
- SKiDL now searches for parts with a user-configurable list of library search paths.
- Part descriptions and keywords are now loaded from the .dcm file associated with a .lib file.
- SKiDL scripts can now output netlists in XML format.
- Added command-line utility to convert netlists into SKiDL programs.
- Changed the link to the documentation.
- First release on PyPI.