sst-it 1.0.2

SST Interoperability Toolkit

SST Interoperability Toolkit

A toolkit to provide interoperability between Structural Simulation Toolkit (SST) and external hardware description languages (HDL).

Table of Contents

• Requirements
• Installation
• Usage
  • Black Box Code Generation
• Supported HDLs
  • PyRTL
  • SystemC
  • Verilog

Requirements

The current stable version of SIT requires:

• SST Core 10.0.0+
• Python 3.6+
• CMake 3.18+
• GNU Make 3+

Additionally, supported HDLs have their own sets of requirements. See

Installation

The toolkit can be installed using pip:

$ pip install sst-it

The Python package ships with the header library required to interoperate with SST. To install the library, run the console script:

$ sit --install

Usage

Black Box Code Generation

To establish interoperability between an SST model and an HDL module, a black box SST component and HDL driver must be generated. The black box establishes the configurations required for the interprocess communication (IPC) between the SST and the external HDL processes.

Supported HDLs

Note: For the sake of simplicity and consistency in the nomenclature, the languages, toolkits or libraries in the following categories will be simply labeled as HDL:

• hardware description languages (SystemVerilog, Verilog, VHDL, etc.)
• hardware level modeling languages (PyRTL, SystemC, etc.)

PyRTL

While PyRTL blackboxes can be generated, they are currently in the alpha stages of development and should not be used in production. Usage of the classes are discouraged, but they can be accessed via:

from sit import SITPyRTL

SystemC

While SystemC blackboxes can be generated, they are currently in the alpha stages of development and should not be used in production. Usage of the classes are discouraged, but they can be accessed via:

from sit import SITSystemC

Verilog

Verilog modules have the following requirements:

• cocotb
• An HDL simulator (such as Icarus Verilog, Verilator, GHDL or other simulator)

from sit import SITVerilog