An SMT-based bounded model checker for signal temporal logic
Project description
STLmc
STLmc is an SMT-based bounded model checker for signal temporal logic (STL) of hybrid systems. The algorithm of the tool is refutationally complete for STL properties of bounded signals.
For more information about STLmc, please visit our website
Features
- Bounded model checking
- Generating trajectories that falsify the given STL properties if any exists
- Supporting various SMT solvers (e.g., Z3, Yices2, dReal3)
Project details
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