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[System]Verilog Module I/O parser and printer

Project description

SVModule

Introduction

SVModule is set of python scripts/classes to parse a [System]Verilog module declaration and paste it as an instance, parameter definitions... It manages module imports, parameters, standard and interface I/O ports.

The objective is to provide a similar behavior of the emacs VHDL mode but in the form of shell commands. Then it is easy to wrap them into your preferred editor as macros or functions.

License

SVModule is distributed under the GPLv3, the complete license description can be found here.

General information

The documentation is available here. Of course, contribution are welcomed.

Project details


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Files for svmodule, version 1.1.2
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