[System]Verilog Module I/O parser and printer
Project description
SVModule
Introduction
SVModule is set of python scripts/classes to parse a [System]Verilog module declaration and paste it as an instance, parameter definitions... It manages module imports, parameters, standard and interface I/O ports.
The objective is to provide a similar behavior of the emacs VHDL mode but in the form of shell commands. Then it is easy to wrap them into your preferred editor as macros or functions.
License
SVModule is distributed under the GPLv3, the complete license description can be found here.
General information
The documentation is available here. Of course, contribution are welcomed.
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| Filename, size | File type | Python version | Upload date | Hashes |
|---|---|---|---|---|
| Filename, size svmodule-1.1.2-py3-none-any.whl (42.5 kB) | File type Wheel | Python version py3 | Upload date | Hashes View |
| Filename, size svmodule-1.1.2.tar.gz (12.7 kB) | File type Source | Python version None | Upload date | Hashes View |
