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Tsfpga is a project platform for modern FPGA development.

Project description

Website Gitlab pypi License Python line coverage VHDL line coverage VHDL branch coverage

Tsfpga is a project platform for modern FPGA development. With its python build/simulation flow, along with complementary VHDL components, it is perfect for CI/CD and test-driven development. Focus has been placed on flexibility and modularization, achieving scalability even in very large multi-vendor code bases.

See documentation on the website: https://tsfpga.com

Key features

  • Source code centric project structure: Build projects, test configurations, constraints, IP cores, etc. are handled “close” to the source code.

  • Complete Vivado build system.

  • Ideal for setting up VUnit simulation projects.

  • Handling of IP cores and simlib for your simulation project, with automatic re-compile when necessary.

  • Register code generation from TOML: VHDL package, HTML documentation, C header, C++ class.

  • VHDL AXI components that enable the register bus: AXI-to-AXI-Lite converter, AXI-Lite interconnect, AXI-Lite mux (splitter), AXI-Lite clock domain crossing, AXI-Lite generic register file.

The maintainers place high focus on quality, with everything having good unit test coverage and a though-out structure. The project is mature and used in many production environments.

License

This project is released under the terms of the BSD 3-Clause License. See license.txt for details.

Project details


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Source Distribution

tsfpga-4.0.1.tar.gz (110.2 kB view hashes)

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