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A package to generate verilog for TNNs

Project description

Twn_Generator v0.1.5

This package generates c or verilog code for convolutions in Ternary Neural Networks


To install run

  pip3 install twn_generator

Example Usage

There are two example verilog use cases for computing the convolution

The first uses 16 bit adders to compute the convolution quickly. The second computes the same result but computes the convolution using 4 bit serial adders. This only has a quarter of the throughput but also a quarter of the area in adders.

To run the CSE and generate the adders, run:

   python3 --matrix_fname data/conv1_weights.csv --cse_fname data/conv1_tern_op_list.csv --module_name lyr1 --BW_in 16
   python3 --matrix_fname data/conv1_weights.csv --cse_fname data/conv1_tern_op_list.csv --module_name lyr1_serial --BW_in 4 --serial

This will generate 3 files:

  • => the 16 bit adder version
  • => the 4 bit serial adder version
  • => a helper module implementing the serial adder

In the verilog/ directory the following can be used to verify the 16 bit adder example:


For the 4 bit serial adder example:

  • from_serial.v
  • to_serial.v

The top level design modules are and respectively. The simulation test sources are and

For more details on CSE

For more details on SMM


The output of the generator ( the verilog or c in this case ) is not under GPL

See: In what cases is the output of a GPL program covered by the GPL too?


Please cite:

  title={Unrolling Ternary Neural Networks},
  author={Tridgell, Stephen and Kumm, Martin and Hardieck, Martin and Boland, David and Moss, Duncan and Zipf, Peter and Leong, Philip HW},
  journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)},

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