Utility for simply creating and modifying VHDL bus slave modules
b”# uart register toolnn. uart does not refer to the hardware device!nn## ConceptnnThe main goal of the project is to able to automatically create and modify VHLD bus slave modules based on a simple definition format. By employing VHDL records the handling of the registers can be completely hidden in a module seperate from the rest of the designers logic. All referring to the registers are done via a record which specifies if the register is read-only or read-write, and also includes the name. All bus-specific signals are also wrapped in records. This increases the readability of the design as a whole.nn## Bus supportnnuart currently supports these bus-types:nn- AXI4-liten nn## Getting Startednn`pip install uart`nnn### Usagenn`uart.py FILE [-o DIR]`nn`uart.py -c FILE [-o DIR]`nn`uart.py -e FILE [-o DIR]`nn`uart.py –version`nn`uart.py -h | –help`n nn### ExamplesnnThe examples folder contain a JSON-file generated by the menu-system. This file is readable to the point that you can create your own from this template alone if you can’t bothered with the menu-system. The folder also contain the output files generated based on the JSON-file.nnn## ContributingnnIf you have ideas on how to improve the project, please review [CONTRIBUTING.md](CONTRIBUTING.md) for details. Note that we also have a [Code of Conduct](CODE_OF_CONDUCT.md). nnn## LicensennThis project is licensed under the MIT license - see [LICENSE](LICENSE) for details.nn”
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