Utility for simply creating and modifying VHDL bus slave modules
Project description
Utility for simply creating and modifying VHDL bus slave modules. uart does not refer to the hardware device!
Concept
The main goal of the project is to able to automatically create and modify VHLD bus slave modules based on a simple definition format. By employing VHDL records the handling of the registers can be completely hidden in a module seperate from the rest of the designers logic. All referring to the registers are done via a record which specifies if the register is read-only or read-write, and also includes the name. All bus-specific signals are also wrapped in records. This increases the readability of the design as a whole.
Bus support
uart currently supports these bus-types:
AXI4-lite
Getting Started
pip install uart
Usage
uart.py FILE [-o DIR]
uart.py -c FILE [-o DIR]
uart.py -e FILE [-o DIR]
uart.py --version
uart.py -h | --help
Examples
The examples folder contain a JSON-file generated by the menu-system. This file is readable to the point that you can create your own from this template alone if you can’t bothered with the menu-system. The folder also contain the output files generated based on the JSON-file.
Contributing
If you have ideas on how to improve the project, please review CONTRIBUTING.md for details. Note that we also have a Code of Conduct.
License
This project is licensed under the MIT license - see LICENSE for details.
Project details
Release history Release notifications | RSS feed
Download files
Download the file for your platform. If you're not sure which to choose, learn more about installing packages.