Utility for simply creating and modifying VHDL bus slave modules
Utility for simply creating and modifying VHDL bus slave modules. uart does not refer to the hardware device!
The main goal of the project is to able to automatically create and modify VHLD bus slave modules based on a simple definition format. By employing VHDL records the handling of the registers can be completely hidden in a module seperate from the rest of the designers logic. All referring to the registers are done via a record which specifies if the register is read-only or read-write, and also includes the name. All bus-specific signals are also wrapped in records. This increases the readability of the design as a whole.
uart currently supports these bus-types:
pip install uart
uart.py FILE [-o DIR]
uart.py -c FILE [-o DIR]
uart.py -e FILE [-o DIR]
uart.py -h | --help
The examples folder contain a JSON-file generated by the menu-system. This file is readable to the point that you can create your own from this template alone if you can’t bothered with the menu-system. The folder also contain the output files generated based on the JSON-file.
This project is licensed under the MIT license - see LICENSE for details.
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