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A library for constructing a Verilog HDL source code in Python

Project description


A library for constructing a Verilog HDL source code in Python

Copyright (C) 2015, Shinya Takamaeda-Yamazaki



Apache License 2.0 (

What’s Veriloggen?

Veriloggen is an open-sourced library for constructing a Verilog HDL source code in Python.

Veriloggen is not a behavior synthesis (or high level synthesis). Veriloggen provides a lightweight abstraction of Verilog HDL AST. You can build up a hardware design written in Verilog HDL very easily by using the AST abstraction and the entire functionality of Python.


  • Python (2.7 or later, 3.3 or later)

  • Pyverilog (Python-based Verilog HDL Design Processing Toolkit)

    • Install from pip: ‘pip install pyverilog’ for Python2.7 or ‘pip3 install pyverilog’ for Python3

    • Install from github into this package: ‘cd Pycoram; git clone; cd pycoram; ln -s ../Pyverilog/pyverilog’

  • Jinja2 (2.7 or later)

  • The code generator uses Jinja2 template engine.

  • ‘pip install jinja2’ (for Python 2.x) or ‘pip3 install jinja2’ (for Python 3.x)


If you want to use Veriloggen as a general library, you can install on your environment by using

If Python 2.7 is used,

python install

If Python 3.x is used,

python3 install

Getting Started

You can find some examples in ‘veriloggen/sample/’.

Let’s begin veriloggen by an example. Create a example Python script in Python as below. A blinking LED hardware is modeled in Python.

import sys
import os

from veriloggen import *
def mkLed():
    m = Module('blinkled')
    width = m.Parameter('WIDTH', 8)
    clk = m.Input('CLK')
    rst = m.Input('RST')
    led = m.OutputReg('LED', width)
    count = m.Reg('count', 32)

             [ If(rst,
                  [ count.set(0) ],
                  [ count.set(count + 1) ])])

             [ If(rst,
                  [ led.set(0) ],
                  [ If(count == 1024 - 1,
                       [ led.set(led + 1) ])])])

    return m

led = mkLed()
verilog = led.toVerilog()

Run the script.


You will have a complete Verilog HDL source code that is generated by a source code generator of Pyverilog. Currently a source code generated by Pyverilog has no good indentation. Please prettify it by using a standard text editor.

module blinkled #
  parameter WIDTH = 8

  input [0:0] CLK,
input [0:0] RST,
output reg [(WIDTH - 1):0] LED

  reg [(32 - 1):0] count;
  always @(posedge CLK)
  if(RST) begin
  count <= 0;
else begin
  count <= (count + 1);
  always @(posedge CLK)
  if(RST) begin
  LED <= 0;
else begin
  if((count == 1023)) begin
  LED <= (LED + 1);


Class and method


is corresponding to ‘module’ in Verilog HDL. The Module class has several class methods to describe signals and assignments.

Module.Input(name, width=None, length=None, signed=False, value=None)

is a class method to add a input port to the module.

Module.Output(name, width=None, length=None, signed=False, value=None)

is a class method to add a output port to the module.

Module.Inout(name, width=None, length=None, signed=False, value=None)

is a class method to add a inout port to the module.

Module.Reg(name, width=None, length=None, signed=False, value=None)

Module.Wire(name, width=None, length=None, signed=False, value=None)

Module.Parameter(name, value, width=None, length=None, signed=False)

Module.Localparam(name, value, width=None, length=None, signed=False)

Module.Always(sensitivity, statement)

Module.Assign(left, right)

Module.Instance(module, instname, params, ports)


Not yet.

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