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  • License: GNU General Public License v3 or later (GPLv3+) (GPLv3+)
  • Author: Michał Kruszewski
  • Tags Bus Interface, Control and Status Registers, Co-simulation, Documentation Generation, Electronic Design Automation, Electronic Systems, Firmware Generation, FPGA, Hardware Design, HDL, Hierarchical Register Description, Memory, Register Addressing, Register Synthesis, RTL, Software Generation, SystemVerilog, VHDL
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Project description

PyWbFBD

Functional Bus Description Language compiler back-end for Wishbone written in Python.

SPDX-License-Identifier: GPL-3.0-or-later

https://spdx.org/licenses/GPL-3.0-or-later.html

Copyright (c) 2021 Michał Kruszewski

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  • License: GNU General Public License v3 or later (GPLv3+) (GPLv3+)
  • Author: Michał Kruszewski
  • Tags Bus Interface, Control and Status Registers, Co-simulation, Documentation Generation, Electronic Design Automation, Electronic Systems, Firmware Generation, FPGA, Hardware Design, HDL, Hierarchical Register Description, Memory, Register Addressing, Register Synthesis, RTL, Software Generation, SystemVerilog, VHDL
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0.0.0

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