https://pypi.org/project/axion-hdl/ Recent updates to the Python Package Index for axion-hdl en https://pypi.org/project/axion-hdl/1.5.1/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 07 May 2026 07:29:18 GMT https://pypi.org/project/axion-hdl/1.5.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 07 May 2026 05:47:51 GMT https://pypi.org/project/axion-hdl/1.4.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Fri, 24 Apr 2026 11:45:20 GMT https://pypi.org/project/axion-hdl/1.3.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 23 Apr 2026 13:18:00 GMT https://pypi.org/project/axion-hdl/1.2.1/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Sat, 11 Apr 2026 11:25:33 GMT https://pypi.org/project/axion-hdl/1.2.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Sat, 11 Apr 2026 09:44:35 GMT https://pypi.org/project/axion-hdl/1.1.3/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Fri, 10 Apr 2026 06:45:52 GMT https://pypi.org/project/axion-hdl/1.1.2/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 05 Feb 2026 20:43:29 GMT https://pypi.org/project/axion-hdl/1.1.1/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 05 Feb 2026 18:56:46 GMT https://pypi.org/project/axion-hdl/1.1.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Sun, 01 Feb 2026 18:00:08 GMT https://pypi.org/project/axion-hdl/1.0.1/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 29 Jan 2026 21:26:00 GMT https://pypi.org/project/axion-hdl/1.0.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 29 Jan 2026 21:06:26 GMT https://pypi.org/project/axion-hdl/0.11.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Tue, 20 Jan 2026 15:52:29 GMT https://pypi.org/project/axion-hdl/0.10.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Fri, 02 Jan 2026 15:20:21 GMT https://pypi.org/project/axion-hdl/0.9.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Wed, 31 Dec 2025 22:41:16 GMT https://pypi.org/project/axion-hdl/0.8.3/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Sat, 27 Dec 2025 17:52:33 GMT https://pypi.org/project/axion-hdl/0.8.2/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Fri, 26 Dec 2025 21:33:26 GMT https://pypi.org/project/axion-hdl/0.8.1/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Fri, 19 Dec 2025 07:46:56 GMT https://pypi.org/project/axion-hdl/0.8.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Mon, 15 Dec 2025 18:23:46 GMT https://pypi.org/project/axion-hdl/0.6.3/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Fri, 12 Dec 2025 11:53:38 GMT https://pypi.org/project/axion-hdl/0.6.2/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Fri, 12 Dec 2025 11:05:44 GMT https://pypi.org/project/axion-hdl/0.4.3/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Tue, 09 Dec 2025 20:45:53 GMT https://pypi.org/project/axion-hdl/0.4.1/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Tue, 09 Dec 2025 17:06:45 GMT https://pypi.org/project/axion-hdl/0.4.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Tue, 09 Dec 2025 11:55:00 GMT https://pypi.org/project/axion-hdl/0.3.1/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 04 Dec 2025 19:23:31 GMT https://pypi.org/project/axion-hdl/0.3.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 04 Dec 2025 10:27:04 GMT https://pypi.org/project/axion-hdl/0.2.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 04 Dec 2025 08:31:56 GMT https://pypi.org/project/axion-hdl/0.1.1/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Thu, 04 Dec 2025 07:31:44 GMT https://pypi.org/project/axion-hdl/0.1.0/ Automated AXI4-Lite Register Interface Generator for VHDL modules bugratufan97@gmail.com Wed, 03 Dec 2025 20:18:08 GMT