https://pypi.org/project/peakrdl-etana/ Recent updates to the Python Package Index for peakrdl-etana en https://pypi.org/project/peakrdl-etana/0.7.0/ Compile SystemRDL into a Verilog control/status register (CSR) block Thu, 08 Jan 2026 00:39:07 GMT https://pypi.org/project/peakrdl-etana/0.6.0/ Compile SystemRDL into a Verilog control/status register (CSR) block Wed, 07 Jan 2026 12:50:42 GMT https://pypi.org/project/peakrdl-etana/0.5.0/ Compile SystemRDL into a Verilog control/status register (CSR) block Sat, 22 Nov 2025 17:08:08 GMT https://pypi.org/project/peakrdl-etana/0.4.0/ Compile SystemRDL into a Verilog control/status register (CSR) block Wed, 12 Nov 2025 12:39:56 GMT https://pypi.org/project/peakrdl-etana/0.3.0/ Compile SystemRDL into a Verilog control/status register (CSR) block Mon, 03 Nov 2025 22:04:22 GMT https://pypi.org/project/peakrdl-etana/0.2.0/ Compile SystemRDL into a Verilog control/status register (CSR) block Tue, 28 Oct 2025 17:10:45 GMT https://pypi.org/project/peakrdl-etana/0.1.0/ Compile SystemRDL into a SystemVerilog control/status register (CSR) block Mon, 27 Oct 2025 23:01:33 GMT https://pypi.org/project/peakrdl-etana/0.0.8/ Compile SystemRDL into a SystemVerilog control/status register (CSR) block Mon, 27 Oct 2025 22:53:18 GMT