with the selected classifier
Collection of interfaces to communicate with laboratory devices, with support for multithreading in PyQt5.
NGSPICE Code Model Testing
Import and export IP-XACT XML to/from the systemrdl-compiler register model
Easy Verilog simulation
Python toolbox for building complex digital hardware
An effective Remote Co-Verification (ReCoVer) library of hardware and software co-designs
PID controller with integral-windup & derivative-kick prevention and bumpless manual-to-auto-mode transfer.
An IP Core Management Infrastructure written in Python - pyIPCMI.
Common utility functions for LibreCell suite.
Library for working with fixed-point numbers in SystemVerilog
Swoop is a Python library for working with CadSoft Eagle files.
Signal and Power Integrity Tools
Read, modify, and create Cadsoft EAGLE files
Meta-package for the LibreCell suite.
Serial communication link bit error rate tester simulator, written in Python.
Pacote Open Source desenvolvido no Brasil para modelar e simular Sistemas Elétricos de Potência. Open Source Package developed in Brazil to model and simulate Electric Power Systems
A tiny Python package to parse spice raw data files
Python Transaction Level Modeling