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Juan Sanchez

Username    devsim
Date joined   Joined

6 projects

devsim

Last released

DEVSIM: TCAD Device Simulator

symdiff

Last released

SYMDIFF: Symbolic differentation of algebraic expressions

osprem

Last released

Coming soon

pyadms

Last released

pyadms: Verilog-A Compiler

tdr-convert

Last released

tdr-convert: tdr file converter

veriloga

Last released

pyadms: Verilog-A Compiler

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