9 projects
substrait-validator
Validator for Substrait query plans
gerbertools
Tools for inspecting and DRC'ing PCBs their Gerber files
vhdre
VHDL code generator for matching regular expressions.
dqcsim-qx
A DQCsim backend for the QX simulator
dqcsim-cqasm
A DQCsim frontend for cQASM files
dqcsim-quantumsim
DQCsim backend for QuantumSim.
dqcsim-openql-mapper
The OpenQL mapper wrapped in a DQCsim operator
vhdeps
VHDL dependency analyzer and simulation driver.
vhdmmio
VHDL code generator for AXI4-lite compatible memory-mapped I/O (MMIO)register files and bus infrastructure.
