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  Joined on Nov 10, 2014

5 projects


Last released on Oct 9, 2017

A library for constructing a Verilog HDL source code in Python


Last released on Oct 7, 2017

IP-core package generator for AXI4/Avalon


Last released on Oct 4, 2017

Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator


Last released on Nov 6, 2015

Python-based Portable IP-core Synthesis Framework for FPGA-based Computing


Last released on Nov 12, 2014

Cycle-Accurate Hardware Simulation Framework on Abstract FPGA Platforms

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