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HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig and the plugins ghdl-yosys-plugin and yosys-slang. It relies on Docker and PyFPGA containers.

  • vhdl2vhdl: converts from a newer VHDL to VHDL'93 (using ghdl).
  • vhdl2vlog: converts from VHDL to Verilog (backends: ghdl or yosys).
  • slog2vlog: converts from SystemVerilog to Verilog (frontends: slang, synlig or yosys).

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Release files for HDLconv 0.3.0

For a detailed explanation of source distributions (sdists) and built distributions (wheels), please see the package formats documentation.

Source distribution (sdist)

Source distribution for HDLconv 0.3.0
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hdlconv-0.3.0.tar.gz 17.8 kB Details

Built distribution (wheel)

Table of built distributions (wheels) for HDLconv 0.3.0
File Interpreter ABI Platform
hdlconv-0.3.0-py3-none-any.whl Python 3 none any Details

Total release size: 37.4 kB

Release files / hdlconv-0.3.0.tar.gz

Download URL hdlconv-0.3.0.tar.gz
Size 17.8 kB
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Release files / hdlconv-0.3.0-py3-none-any.whl

Download URL hdlconv-0.3.0-py3-none-any.whl
Size 19.6 kB
Tags Python 3
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Uploaded via twine/6.1.0 CPython/3.12.9

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This release

0.3.0 This release

2 release files

0.2.0

2 release files

0.1.1

2 release files

0.1.0

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