logikbench 0.1.0

Parameterized RTL benchmark suite

LogikBench

119 parametrized RTL benchmarks for unbiased EDA evaluation

Problem

The semiconductor industry lacks a comprehensive, standardized benchmark suite for evaluating EDA tools, design flows, foundry processes, and FPGA devices. Existing RTL benchmark suites suffer from critical gaps:

• Small datasets with limited coverage
• Hard-coded circuit sizes preventing parametric studies
• Limited circuit diversity that doesn't reflect real designs
• Ambiguous licenses blocking commercial use
• No execution infrastructure for reproducible results
• No standard metrics for comparing tools and flows
• No standard datasets (no "ImageNet for EDA")
• No standard scores (no "SpecInt/Dhrystone for EDA")
• Limited provenance on benchmark origins and design intent

These gaps make it difficult to objectively compare tools, validate improvements, and track progress across the industry.

Solution

LogikBench provides a comprehensive, parametrized RTL benchmark suite with:

• 119 unique benchmark circuits spanning basic logic to complex subsystems
• 10,000+ configurations through parameter sweeping
• MIT License enabling commercial and academic use
• Python API built on SiliconCompiler for easy integration
• Standardized metrics and execution infrastructure
• Full provenance with clear documentation and design intent
• Active development with continuous additions to the suite

The suite covers five major categories targeting different evaluation needs:

Group	Benchmarks	Description
basic	22	Logic primitives and combinational blocks
arithmetic	33	Arithmetic operators and datapaths
memory	13	Memory structures and storage elements
blocks	31	Complex subsystems and IP blocks
epfl	20	EPFL arithmetic and control benchmarks

Benchmark Inventory

Basic Logic (22 benchmarks)

Benchmark	Description	Verilog
arbiter	Priority arbiter	arbiter.v
band	Bitwise AND	band.v
bbuf	Buffer	bbuf.v
bin2gray	Binary to Gray code converter	bin2gray.v
bin2prio	Binary to priority encoder	bin2prio.v
binv	Bitwise inverter	binv.v
bnand	Bitwise NAND	bnand.v
bnor	Bitwise NOR	bnor.v
bor	Bitwise OR	bor.v
bxnor	Bitwise XNOR	bxnor.v
bxor	Bitwise XOR	bxor.v
crossbar	Crossbar switch	crossbar.v
dffasync	Asynchronous reset flip-flop	dffasync.v
dffsync	Synchronous reset flip-flop	dffsync.v
gray2bin	Gray to binary code converter	gray2bin.v
mux	Multiplexer	mux.v
muxcase	Case-based multiplexer	muxcase.v
muxhot	One-hot multiplexer	muxhot.v
muxpri	Priority multiplexer	muxpri.v
onehot	One-hot encoder	onehot.v
pipeline	Pipeline register	pipeline.v
shiftreg	Shift register	shiftreg.v

Arithmetic (33 benchmarks)

Benchmark	Description	Verilog
abs	Absolute value	abs.v
absdiff	Absolute difference	absdiff.v
absdiffs	Signed absolute difference	absdiffs.v
add	Adder	add.v
addsub	Adder-subtractor	addsub.v
cmp	Comparator	cmp.v
counter	Counter	counter.v
csa32	3:2 carry-save adder	csa32.v
csa42	4:2 carry-save adder	csa42.v
dec	Decrementer	dec.v
dotprod	Dot product	dotprod.v
inc	Incrementer	inc.v
log2	Log base 2	log2.v
mac	Multiply-accumulate	mac.v
max	Maximum	max.v
min	Minimum	min.v
mul	Multiplier	mul.v
muladd	Multiply-add	muladd.v
muladdc	Multiply-add with carry	muladdc.v
mulc	Constant multiplier	mulc.v
mulreg	Registered multiplier	mulreg.v
muls	Signed multiplier	muls.v
relu	ReLU activation function	relu.v
round	Rounder	round.v
shiftar	Arithmetic right shift	shiftar.v
shiftb	Barrel shifter	shiftb.v
shiftl	Left shift	shiftl.v
shiftr	Right shift	shiftr.v
sine	Sine function	sine.v
sqdiff	Squared difference	sqdiff.v
sqrt	Square root	sqrt.v
sub	Subtractor	sub.v
sum	Summation tree	sum.v

Memory (13 benchmarks)

Benchmark	Description	Verilog
axiram	AXI RAM interface	axiram.v
cache	Cache memory	cache.v
fifoasync	Asynchronous FIFO	fifoasync.v
fifosync	Synchronous FIFO	fifosync.v
ramasync	Asynchronous RAM	ramasync.v
rambit	Bit-wide RAM	rambit.v
rambyte	Byte-wide RAM	rambyte.v
ramdp	Dual-port RAM	ramdp.v
ramsdp	Simple dual-port RAM	ramsdp.v
ramsp	Single-port RAM	ramsp.v
ramspnc	Single-port RAM (no change)	ramspnc.v
regfile	Register file	regfile.v
rom	Read-only memory	rom.v

Complex Blocks (31 benchmarks)

Benchmark	Description	Verilog
aes	AES encryption	aes.v
apbregs	APB register block	apbregs.v
axicrossbar	AXI crossbar	axicrossbar.v
axidev	AXI device	axidev.v
axihost	AXI host	axihost.v
conv2d	2D convolution engine	conv2d.v
en8b10b	8b/10b encoder	en8b10b.v
ethmac	Ethernet MAC	ethmac.v
fft	Fast Fourier Transform	fft.v
firfix	Fixed-point FIR filter	firfix.v
firprog	Programmable FIR filter	firprog.v
fpu32	32-bit floating-point unit	fpu32.v
fpu64	64-bit floating-point unit	fpu64.v
hamming	Hamming encoder/decoder	hamming.v
i2c	I2C controller	i2c.v
ialu	Integer ALU	ialu.v
ibex	Ibex RISC-V core	ibex.v
lfsr	Linear feedback shift register	lfsr.v
matmul	Matrix multiplication	matmul.v
median3x3	3x3 median filter	median3x3.v
nvdla	NVIDIA Deep Learning Accelerator	nvdla.v
ofdm	OFDM modulator	ofdm.v
picorv32	PicoRV32 RISC-V core	picorv32.v
sad8x8	8x8 sum of absolute differences	sad8x8.v
serv	SERV bit-serial RISC-V core	serv.v
sobel3x3	3x3 Sobel filter	sobel3x3.v
spi	SPI controller	spi.v
uart	UART	uart.v
umihost	UMI host interface	umihost.v
umiregs	UMI register block	umiregs.v
viterbi	Viterbi decoder	viterbi.v

EPFL Benchmarks (20 benchmarks)

Benchmark	Description	Verilog
adder	EPFL adder benchmark	adder.v
arbiter	EPFL arbiter benchmark	arbiter.v
bar	Barrel shifter	bar.v
cavlc	CAVLC encoder	cavlc.v
dec	Decoder	dec.v
div	Divider	div.v
hyp	Hypotenuse calculator	hyp.v
i2c	I2C controller	i2c.v
int2float	Integer to float converter	int2float.v
log2	Log base 2	log2.v
max	Maximum	max.v
mem_ctrl	Memory controller	mem_ctrl.v
multiplier	Multiplier	multiplier.v
priority	Priority encoder	priority.v
router	Router	router.v
sin	Sine function	sin.v
sqrt	Square root	sqrt.v
square	Square function	square.v
voter	Voter circuit	voter.v

Usage

Each LogikBench benchmark circuit consists of:

• Tech-agnostic RTL Verilog files for broad tool compatibility
• SiliconCompiler Design object with metadata and configuration

The SiliconCompiler Design object captures benchmark data as files, parameters, topmodule name, and other settings grouped as a fileset. Every circuit in the LogikBench suite has a Python class that inherits from SiliconCompiler's Design class, as shown in this mux example:

from os.path import dirname, abspath
from siliconcompiler import Design

class Mux(Design):
    def __init__(self):
        name = 'mux'
        fileset = 'rtl'
        rootname = f'{name}_root'
        super().__init__(name)
        self.set_dataroot(rootname, dirname(abspath(__file__)))
        self.add_file(f'rtl/{name}.v', fileset, dataroot=rootname)
        self.set_topmodule(name, fileset)

To use a benchmark circuit, simply instantiate its class. You then have access to all methods inherited from SiliconCompiler. The example below shows how to instantiate the Mux circuit and write out its RTL settings in a standard filelist format that can be read directly by tools like Icarus Verilog, Verilator, and slang.

import logikbench as lb
d = lb.basic.Mux()
d.write_fileset('mux.f', fileset='rtl')

Prerequisites

You will need properly installed synthesis tools installed to run benchmarks. Follow the install instructions for indidivual repos to properly install plugins. There is no dependency linkage between yosys and plugins. The recommendation is to isntall everything cleanly and to use versions from main. In Ubuntu, shared yosys libraries are placed at /usr/local/share/yosys/plugins/*.so

• Yosys - Open-source synthesis tool
• Yosys-slang - SystemVerilog frontend plugin
• Wildebeest

Installation

Install logikbench via PyPI:

pip install logikbench

Developers should clone the repo and install package locally as shown below.

git clone https://github.com/zeroasiccorp/logikbench
cd logikbench
pip install --upgrade pip
pip install -e .

Running Benchmarks

LogikBench includes the lb command-line tool for batch processing benchmarks. It drives synthesis through SiliconCompiler: each benchmark is a SiliconCompiler Design, and --target selects what runs.

Targets:

• (no --target) — FPGA synthesis via LogikBench's lbflow (Yosys synth_fpga).
• freepdk45 — ASIC synthesis + OpenSTA timing via lbflow (pre-layout STA, so it reports fmax without place & route).
• <pdk>_demo (freepdk45_demo, asap7_demo, skywater130_demo, gf180_demo, ihp130_demo) — the official SiliconCompiler demo target for that PDK, run through SC's asicflow (full RTL→GDS). Use --stop to limit how far it runs.

--start/--stop restrict the run to a step range, named by stage: synthesis, floorplan, place, cts, route (each mapped to the appropriate SC node). For example --stop synthesis runs synthesis only.

By default lb synthesizes the selected benchmarks and records metrics; pass --collect_only to read metrics from existing build results without synthesizing. Run lb -h to see all available options.

Options

Flag	Description
-g, --group	Benchmark group(s) to run: basic, memory, arithmetic, epfl, blocks (required)
-n, --name	Only run benchmark(s) with these name(s); matched against the benchmarks in the selected group(s), so each runs in whichever group defines it (default: all of them)
--target	ASIC target: a PDK name (freepdk45, runs lbflow) or a <pdk>_demo name (runs the SC demo target via asicflow). Omit for FPGA synthesis
--start / --stop	First / last stage to run: synthesis, floorplan, place, cts, route (default: full flow)
-b, --builddir	Build directory root; per-benchmark work goes in <builddir>/<target>/<name> (target is the --target name, or fpga when none; default root: build)
-o, --output	Results file; .json or .csv selected by extension (default: <builddir>/<target>/results.json)
-j, --jobs	Number of benchmarks to synthesize in parallel (default: 1); each is an independent SiliconCompiler run, fanned out over a process pool
--incremental	Skip benchmarks whose build already completed successfully; only synthesize the rest
--collect_only	Read metrics from existing build results without synthesizing
-v, --verbose	Show full SiliconCompiler tool/scheduler logs (quieted by default)

Metrics are fixed by the run mode: cells, luts, nets, pins, tasktime for FPGA; cells, cellarea, fmax, setupslack for ASIC.

By default each run removes the benchmark's build directory beforehand, so synthesis always runs fresh (no SiliconCompiler build reuse). Use --incremental to skip benchmarks already completed, or --collect_only to read metrics from existing builds without synthesizing.

Examples

Synthesize all benchmarks in a group and export metrics to JSON:

lb -g arithmetic -o results.json

Run several groups at once:

lb -g basic arithmetic memory -o results.json

Run a single benchmark into a CSV:

lb -g basic -n binv -o results.csv

Run a group 8 benchmarks at a time (job-level parallelism):

lb -g basic -j 8 -o results.json

Collect metrics from an already-synthesized run (no synthesis):

lb -g basic --collect_only -o results.csv

Run ASIC synthesis + timing (lbflow) on the freepdk45 PDK:

lb -g basic --target freepdk45 -o results.csv

Run the asap7 demo target (SC asicflow), synthesis only:

lb -g basic --target asap7_demo --stop synthesis -o results.csv

Contributing

Contributions are welcome! To contribute:

1. Fork the repository
2. Create a feature branch (git checkout -b feature/new-benchmark)
3. Add your benchmark following the existing structure
4. Ensure your code passes linting (flake8)
5. Add tests for your benchmark
6. Submit a pull request

When adding new benchmarks:

• Use parameterizable Verilog for flexibility
• Include a Python wrapper class inheriting from Design
• Add documentation and test cases
• Follow the naming conventions in existing benchmarks

Support

• Issues: GitHub Issues
• Discussions: GitHub Discussions
• Documentation: See individual benchmark READMEs in each category folder

License

The LogikBench project is licensed under the MIT license unless specified otherwise inside the individual benchmark folders.