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TODO: Library of components based on Python and MyHDL

Project description

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A MyHDL library of generic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc. All components are tested with Icarus Verilog simulator.

Work in progres …

Documentation (WiP) is available at: https://github.com/nkavaldj/myhdl_lib/wiki

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