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An infrastructure for implementing chip design flows

Project description

Efabless OpenLane 2 is in early access and all APIs are, presently, highly unstable and subject to change without notice.

If you don't know why you're here, you're probably looking for the stable version of OpenLane at https://github.com/The-OpenROAD-Project/OpenLane.

OpenLane

License: Apache 2.0 Python 3.8 or higher Code Style: black Checked with mypy Built with Nix

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OpenLane is a RTL to GDSII infrastructure library based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for design exploration and optimization. A reference flow performs all ASIC implementation steps from RTL all the way down to GDSII.

You can find the documentation here to get started.

from openlane import Flow

Classic = Flow.get("Classic")

flow = Classic.init_with_config(
    {
        "PDK": "sky130A",
        "DESIGN_NAME": "spm",
        "VERILOG_FILES": ["./src/spm.v"],
        "CLOCK_PORT": "clk",
        "CLOCK_PERIOD": 10,
    },
    design_dir=".",
)

flow.start()

Installation

Binary Dependencies

You'll need the following:

Docker

Works for Windows, macOS and Linux. Easier to set up, but less integrated with your filesystem. Recommended for general users.

See Docker-based installation in the docs.

Do note you'll need to add --dockerized to most CLI invocations of OpenLane.

Nix

Works for macOS and Linux. A bit more complex to set up, but more integrated with your filesystem and overall less upload and download deltas.

See Nix-based installation in the docs.

Conda

TBA

Python-only Installation

You'll need to bring your own compiled tools, but otherwise, simply install OpenLane as follows:

python3 -m pip install --upgrade openlane

Usage

In the root folder of the repository with the venv activated, you may invoke:

python3 -m openlane --pdk-root <path/to/pdk> </path/to/config.json>

To start with, you can try:

python3 -m openlane --pdk-root $HOME/.volare ./designs/spm/config.json

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