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Graham Power

Username    GNPower
Date joined   Joined

3 projects

jig-dsl

Last released

A test language and harness for firmware running on the Renode emulator

PyHDC

Last released

A Python library for Hyperdimensional Computing

VeriGen

Last released

A Python library for generating synthesizable Verilog or SystemVerilog code using the Jinja2 template engine
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