74 projects
ivpm
IVPM (Integrated View Package Manager) is a project-local polyglot package manager.
pssparser
Provides a PSS parser and related tools
pssc
PSSC — the PSS compiler: PSS source to SystemVerilog, C, and Python via Zuspec IR
zuspec-be-sw
Zuspec unified compiled-C backend (software, TLM, and RTL)
zuspec-be-sv
Zuspec SystemVerilog backend
zuspec-dataclasses
None
zuspec-be-py
Zuspec live-Python backend: Zuspec IR to executable Python (zdc) classes
zuspec-ir-core
Zuspec core intermediate representation
dv-solve
Domain-agnostic CLP(FD) constraint solver
pssfmt
A formatter for the Accellera Portable Test and Stimulus Standard (PSS)
debug-mgr
Simple debug manager for use of C++ Python extensions
dv-flow-libhdlsim
Provides dv-flow tasks for performing common tasks related to HDL simulation
pyastbuilder
Utility for generating AST classes from a yaml description
covsight
Coverage analysis CLI and tooling built on covsight-core
covsight-core
Core UCIS data-model API and NCDB format for coverage data
pygments-pss
Pygments lexer for the Accellera Portable Test and Stimulus Standard (PSS)
sphinx-systemverilog
Sphinx autodoc extension for SystemVerilog, powered by the pyslang parser
pyhdl-if
Python interface for HDL programming interfaces
agent-skills-systemrdl
Hierarchical SystemRDL 2.0 authoring reference for coding agents, packaged as an agent skill.
peakrdl-fw-hdl
Generate Featherweight-HDL register descriptions from compiled SystemRDL input
peakrdl-pss
Generate a PSS (Portable Test and Stimulus) register package from SystemRDL
dv-flow-mgr
DV Flow Manager - Data-driven, parameterizable workflow orchestration
dv-flow-libcocotb
DV Flow Manager tasks for building and running cocotb testbenches
dv-flow-libformal
Provides dv-flow tasks for formal verification (skeleton)
ivpm-build
Build helpers and PEP 517 backend for IVPM-managed Python extension projects
pyvsc
pyvsc (Verification Stimulus and Coverage) is a Python package for generating randomized stimulus and defining and collecting functional coverage.
zuspec
None
zuspec-fe-pss
PSS AST to Zuspec IR translation built on pssparser
ciostream
Provides C++ iostream Cython wrappers
pyucis
PyUCIS provides a Python API for manipulating UCIS coverage data.
dv-flow-libgh
DV Flow task library for GitHub REST and GraphQL APIs
dv-flow-liborfs
DV Flow tasks for the OpenROAD RTL-to-GDS flow (ORFS)
dv-flow-librdl
Provides dv-flow tasks for performing common SystemRDL operations via PeakRDL
dv-flow-libfusesoc
DV Flow extension for FuseSoC core management and Edalize tool integration
svdep
Checks whether SystemVerilog need to be recompiled
pytest-dfm
pytest-dfm provides a pytest integration for DV Flow Manager, a build system for silicon design
PyBoolector
Python wrapper around the Boolector SMT solver
zuspec-fe-parser
Provides a PSS parser and related tools
zuspec-arl-dm
Core ARL data model library
vsc-dm
Core Verification Stimulus and Coverage library
fltools
Provides utilities for working with EDA Filelists
dv-flow-libcc
Tasks for building artifacts from C/C++ code
vsc-solvers
Core Verification Stimulus and Coverage library
pyapi-compat-if
Core Verification Stimulus and Coverage library
pytest-fv
pytest extensions to support running functional-verification jobs
zuspec-parser
Provides a PSS parser and related tools
zuspec-arl-eval
Core ARL data model library
dv-flow-libide
Provides dv-flow tasks for maintaining IDE-integration files
dv-flow-libpss
Provides dv-flow tasks for performing common tasks related to Accellera PSS
zuspec-sv
Core ARL data model library
mkdv
mkdv is a Makefile-based mechanism for running Design Verification tools with a Python regression runner
zuspec-cli
Co-specification of hardware, software, design, and test behavior
dv-flow-libhdlim
Provides dv-flow tasks for performing common tasks related to HDL simulation
pyvsc-dataclasses
Front-end for capturing Verification Stimulus and Coverage constructs using dataclasses
jitcc
Supports compiling and running C code on the fly
pyhdl-call-if
Python interface for HDL programming interfaces
pyhdl-tlm-if
Python interface for HDL programming interfaces
pyhdl-pi-if
Python interface for HDL programming interfaces
pytypeworks
PyTypeWorks provides utilities for decorator-driven type manipulation and introspection.
zuspec-py
Co-specification of hardware, software, design, and test behavior
pss-scrambler
PSS Scrambler replaces user-specified identifiers with random names.
libarl
Core ARL model evaluator library
libvsc
Core Verification Stimulus and Coverage library
pyarl-dataclasses
Front-end for capturing Action Relation Level models using dataclasses
vte
Template-driven content generation script focused on verification
tblink-rpc-core
Provides the core TbLink-RPC library
tblink-rpc-hdl
Provides a TbLink-RPC integration for HDL environments
pyucis-viewer
PyUCIS Viewer QT5-based viewer for UCIS data.
pygraphviz-bin
Pre-compiled GraphViz wrapped in Python
vlsim
vlsim is a wrapper around Verilator that adds in a simple C++ front-end for clock generation and trace control
pyyaml-srcinfo-loader
Provides a loader for PyYAML that annotates source info on returned elements
py-vsc
py-vsc (Verification Stimulus and Coverage) is a Python package for generating randomized stimulus and defining and collecting functional coverage.
pybfms-generic-sram
pybfms_generic_sram provides bus functional models for the SRAM protocols
pybfms
PyBFMs provides core libraries and scripts to support Python BFMs driving HDL environments
