53 projects
vsc-dm
Core Verification Stimulus and Coverage library
dv-flow-libhdlsim
Provides dv-flow tasks for performing common tasks related to HDL simulation
dv-flow-mgr
DV Flow Manager is a build system for silicon design
vsc-solvers
Core Verification Stimulus and Coverage library
zuspec-be-sw
Backend library to generate software output
zuspec-fe-parser
Provides a PSS parser and related tools
zuspec-arl-dm
Core ARL data model library
pyapi-compat-if
Core Verification Stimulus and Coverage library
pyhdl-if
Python interface for HDL programming interfaces
pytest-fv
pytest extensions to support running functional-verification jobs
pytest-dfm
pytest-dfm provides a pytest integration for DV Flow Manager, a build system for silicon design
zuspec-parser
Provides a PSS parser and related tools
pyvsc
pyvsc (Verification Stimulus and Coverage) is a Python package for generating randomized stimulus and defining and collecting functional coverage.
ivpm
IVPM (IP and Verification Package Manager) is a project-internal package manager.
zuspec-arl-eval
Core ARL data model library
dv-flow-libide
Provides dv-flow tasks for maintaining IDE-integration files
dv-flow-libpss
Provides dv-flow tasks for performing common tasks related to Accellera PSS
zuspec-sv
Core ARL data model library
pyastbuilder
Utility for generating AST classes from a yaml description
mkdv
mkdv is a Makefile-based mechanism for running Design Verification tools with a Python regression runner
zuspec-be-py
Co-specification of hardware, software, design, and test behavior
debug-mgr
Simple debug manager for use of C++ Python extensions
ciostream
Provides C++ iostream Cython wrappers
svdep
Checks whether SystemVerilog need to be recompiled
pyucis
PyUCIS provides a Python API for manipulating UCIS coverage data.
zuspec-cli
Co-specification of hardware, software, design, and test behavior
zuspec-dataclasses
Front-end for capturing Action Relation Level models using dataclasses
dv-flow-libhdlim
Provides dv-flow tasks for performing common tasks related to HDL simulation
pyvsc-dataclasses
Front-end for capturing Verification Stimulus and Coverage constructs using dataclasses
zuspec
None
PyBoolector
Python wrapper around the Boolector SMT solver
jitcc
Supports compiling and running C code on the fly
pyhdl-call-if
Python interface for HDL programming interfaces
pyhdl-tlm-if
Python interface for HDL programming interfaces
pyhdl-pi-if
Python interface for HDL programming interfaces
pytypeworks
PyTypeWorks provides utilities for decorator-driven type manipulation and introspection.
zuspec-py
Co-specification of hardware, software, design, and test behavior
pss-scrambler
PSS Scrambler replaces user-specified identifiers with random names.
libarl
Core ARL model evaluator library
libvsc
Core Verification Stimulus and Coverage library
pyarl-dataclasses
Front-end for capturing Action Relation Level models using dataclasses
fltools
Provides utilities for working with EDA Filelists
vte
Template-driven content generation script focused on verification
tblink-rpc-core
Provides the core TbLink-RPC library
tblink-rpc-hdl
Provides a TbLink-RPC integration for HDL environments
pyucis-viewer
PyUCIS Viewer QT5-based viewer for UCIS data.
pygraphviz-bin
Pre-compiled GraphViz wrapped in Python
vlsim
vlsim is a wrapper around Verilator that adds in a simple C++ front-end for clock generation and trace control
pyyaml-srcinfo-loader
Provides a loader for PyYAML that annotates source info on returned elements
pssparser
pssparser provides an Accellera PSS parser implemented with ANTLR and Python
py-vsc
py-vsc (Verification Stimulus and Coverage) is a Python package for generating randomized stimulus and defining and collecting functional coverage.
pybfms-generic-sram
pybfms_generic_sram provides bus functional models for the SRAM protocols
pybfms
PyBFMs provides core libraries and scripts to support Python BFMs driving HDL environments
