The yavs VHDL simulator for VUnit, as a VUnit package
Third-party VUnit verification components: VHDL pin timing, Python verification semantics.
Catch VHDL bugs before simulation: a fast Rust formatter and linter with VSG-compatible rules and configuration.
corvidex-mcp: an RTL-centric RAG and indexing MCP
Anthropic, PBC
Visionary sponsor
Bloomberg
Visionary sponsor
Hudson River Trading
Visionary sponsor
Meta
Visionary sponsor
NVIDIA
Visionary sponsor
Microsoft
Sustainability sponsor
Depot
Continuous Integration
AWS
Cloud computing and Security Sponsor
Datadog
Monitoring
Fastly
CDN
Google
Download Analytics
Sentry
Error logging
StatusPage
Status page